Shift register and method of driving shift register

Patent metadata

Field	Value
Publication number	US-2016019828-A1
Application number	US-201514803126-A
Country	US
Kind code	A1
Filing date	Jul 20, 2015
Priority date	Jul 18, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.

First claim

What is claimed is:

1 . A shift register comprising a plurality of stages of shift register circuit, wherein each stage of shift register circuit comprises:
a first switch having a first terminal for receiving a clock signal, a second terminal for outputting a first scan signal of current stage of shift register circuit, and a control terminal electrically coupled to a node of the current stage of shift register circuit; an input circuit comprising:
a second switch having a first terminal, a second terminal electrically coupled to the node of the current stage of shift register circuit, and a control terminal electrically coupled to a node of a previous M-th stage of shift register circuit in the plurality of stages of shift register circuit, wherein M is a positive integer; and
a receiving circuit electrically coupled to the first terminal of the second switch, for receiving a scan signal outputted from the previous M-th stage of shift register circuit, and for controlling a voltage level of the first terminal of the second switch according to the scan signal;
a pull-down circuit electrically coupled to the node of the current stage of shift register circuit and for pulling down a voltage level of the node of the current stage of shift register circuit according to a scan signal outputted from a following L-th stage of shift register circuit in the plurality of stages of shift register circuit, wherein L is a positive integer; and a pull-down voltage regulator circuit electrically coupled to the node of the current stage of shift register circuit and the second terminal of the first switch and for pulling down a voltage level of the second terminal of the first switch according to the voltage level of the node of the current stage of shift register circuit.

2 . The shift register of claim 1 , wherein each stage of shift register circuit further comprises:
a third switch having a first terminal for receiving the clock signal, a second terminal for outputting a second scan signal, and a control terminal electrically coupled to the node of the current stage of shift register circuit; wherein the receiving circuit for receiving the scan signal outputted from the previous M-th stage of shift register circuit is to receive a first scan signal outputted from the previous M-th stage of shift register circuit or a second scan signal outputted from the previous M-th stage of shift register circuit, and the pull-down circuit for pulling down the voltage level of the node of the current stage of shift register circuit according to the scan signal outputted from the following L-th stage of shift register circuit is to receive a first scan signal outputted from the following L-th stage of shift register circuit or a second scan signal outputted from the following L-th stage of shift register circuit.

3 . The shift register of claim 1 , wherein the pull down circuit of each stage of shift register circuit comprises:
a fourth switch having a first terminal electrically coupled to the node of the current stage of shift register circuit, a second terminal electrically coupled to the second terminal of the first switch, and a control terminal; a capacitor having a first terminal for receiving the clock signal and a second terminal electrically coupled to the control terminal of the fourth switch; and a fifth switch having a first terminal for receiving the scan signal outputted from the following L-th stage of shift register circuit, a second terminal electrically coupled to the second terminal of the capacitor, and a control terminal electrically coupled to the first terminal of the fifth switch.

4 . A shift register comprising a plurality of stages of shift register circuit, wherein each stage of shift register circuit comprises:
an input circuit for receiving a scan signal outputted from a previous M-th stage of shift register circuit and for pulling up a voltage level of a node of current stage of shift register circuit according to the scan signal; a first switch having a first terminal for receiving a clock signal, a second terminal for outputting a first scan signal of the current stage of shift register circuit, and a control terminal electrically coupled to the node of the current stage of shift register circuit; a pull-down circuit comprising:
a second switch having a first terminal electrically coupled to the node of the current stage of shift register circuit, a second terminal electrically coupled to the second terminal of the first switch, and a control terminal;
a pull-down controlling circuit for receiving the clock signal and a scan signal outputted from a following L-th stage of shift register circuit and for controlling a voltage level of the control terminal of the second switch according to the clock signal and the scan signal outputted from the following L-th stage of shift register circuit, wherein L is a positive integer; and
a first pull-down voltage regulator circuit electrically coupled to the node of the current stage of shift register circuit, the second terminal of the first switch and a node of the following L-th stage of shift register circuit, and for pulling down a voltage level of the second terminal of the first switch according to the voltage level of the node of the current stage of shift register circuit and a voltage level of the node of the following L-th stage of shift register circuit.

5 . The shift register of claim 4 , wherein each stage of shift register circuit further comprises:
a third switch having a first terminal for receiving the clock signal, a second terminal for outputting a second scan signal, and a control terminal electrically coupled to the node of the current stage of shift register circuit; wherein the input circuit for receiving the scan signal outputted from the previous M-th stage of shift register circuit is to receive a first scan signal outputted from the previous M-th stage of shift register circuit or a second scan signal outputted from the previous M-th stage of shift register circuit, and the pull-down controlling circuit for receiving the scan signal outputted from the following L-th stage of shift register circuit is to receive a first scan signal outputted from the following L-th stage of shift register circuit or a second scan signal outputted from the following L-th stage of shift register circuit.

6 . The shift register of claim 4 , wherein the input circuit comprises:
a fourth switch having a first terminal, a second terminal electrically coupled to the node of the current stage of shift register circuit, and a control terminal electrically coupled to a node of the previous M-th stage of shift register circuit; and a receiving circuit for receiving the scan signal outputted from the previous M-th stage of shift register circuit, and for reducing a voltage level difference between the first terminal of the fourth switch and the node of the current stage of shift register circuit and for making a voltage level of the control terminal of the fourth switch equal to a voltage level of the first terminal of the fourth switch when the first scan signal is of the high voltage level.

7 . The shift register of claim 4 , wherein the pull-down controlling circuit comprises:
a capacitor having a first terminal for receiving the clock signal and a second terminal electrically coupled to the control terminal of the second switch; and a fifth switch having a first terminal for receiving the scan signal outputted from the following L-th stage of shift register circuit, a second terminal electrically coupled to the second terminal of the capacitor, and a control terminal electrically coupled to the first terminal of the fifth switch.

8 . The shift register of claim 4 , further co

Assignees

• Au Optronics Corp

Inventors

• Lin Wei-Li
• Tung Che-Wei
• Chen Chia-Heng

Classifications

• G09G2320/0219

  Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title