Device Isolator with Reduced Parasitic Capacitance

Patent metadata

Field	Value
Publication number	US-2016300907-A1
Application number	US-201514680211-A
Country	US
Kind code	A1
Filing date	Apr 7, 2015
Priority date	Apr 7, 2015
Publication date	Oct 13, 2016
Grant date	—

Abstract

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

First claim

1 . An isolator structure in an integrated circuit formed at a semiconducting surface of a substrate, comprising:
a first buried doped layer of a first conductivity type disposed within a substrate of a second conductivity type, the first buried doped layer having an upper surface beneath the surface; a first tank region of the second conductivity type overlying a portion of the first buried doped layer; a first well region of the first conductivity type disposed at the surface of the substrate and overlying a portion of the first tank region; a first boundary doped region of the first conductivity type disposed at the surface and laterally surrounding the first tank region, the first boundary doped region extending into the surface and contacting the first buried doped layer; a first conductor element disposed near the surface at a location overlying the first well region, separated therefrom by dielectric material; and a second conductor element disposed near the surface at a location overlying the first conductor element, separated therefrom by dielectric material.

2 . The structure of claim 1 , wherein the first and second conductor elements each comprise a capacitor plate.

3 . The structure of claim 1 , wherein the first and second conductor elements each comprise an inductor coil.

4 . The structure of claim 1 , wherein an external terminal of the integrated circuit is electrically connected to the second conductor element.

5 . The structure of claim 1 , further comprising:
a first doped region of the second conductivity type formed at a location of the surface within the first tank region; a second doped region of the second conductivity type formed at a location of the surface of the substrate outside of the first boundary doped region relative to the first well region; a first conductor element in electrical contact with the first doped region, for applying a bias voltage to the tank region; and a second conductor element in electrical contact with the second doped region, for applying a bias voltage to the substrate.

6 . The structure of claim 5 , wherein the plurality of conductor elements further comprises:
a third conductor element, in electrical contact with the first well region for applying a bias voltage to the first well region; and a fourth conductor element, in electrical contact with the first boundary doped region, for applying a bias voltage to the first boundary doped region.

7 . The structure of claim 6 , further comprising:
a plurality of resistors formed into the integrated circuit, each coupled in series with one of the first, second, third, and fourth conductor elements.

8 . The structure of claim 7 , wherein the first conductivity type is n-type and the second conductivity type is p-type;
and wherein the bias voltage applied by the third and fourth conductor elements to the first well region and the first boundary doped region via corresponding resistors is higher than the bias voltage applied by the first and second conductor elements to the first tank region and the substrate via corresponding resistors.

9 . The structure of claim 6 , wherein the first conductivity type is n-type and the second conductivity type is p-type;
and wherein the bias voltage applied by the third and fourth conductor elements to the first well region and the first boundary doped region is higher than the bias voltage applied by the first and second conductor elements to the first tank region and the substrate.

10 . The structure of claim 1 , wherein the first boundary doped region comprises:
a first buried isolation doped region, formed into the substrate at a depth beneath the surface and contacting the first buried doped layer; and a second well region disposed at the surface of the substrate, and overlying and contacting the first buried isolation doped region.

11 . The structure of claim 1 , further comprising:
a second tank region of the second conductivity type underlying the first buried doped layer and surrounding the first boundary doped region; a second buried doped layer of the first conductivity type underlying the second tank region; and a second boundary doped region of the first conductivity type disposed at the surface and laterally surrounding the second tank region, the second boundary doped region extending into the surface and contacting the second buried doped layer.

12 . A method of forming an integrated circuit including an isolator structure at a semiconducting surface of a substrate, comprising:
forming a buried doped layer of a first conductivity type into the substrate, the substrate having a second conductivity type; forming a buried isolation region of the first conductivity type into the substrate so as to contact the buried doped layer; forming a plurality of well regions of the first conductivity type at the surface of the substrate, a first one of the well regions formed into a tank region of the second conductivity type disposed above the buried doped layer and surrounded by the buried isolation region, and a second one of the well regions overlying and in contact with the buried isolation region; then forming a first dielectric layer over the surface; forming a first conductor element overlying the first dielectric layer at a location overlying the first well region; forming a second dielectric layer over the surface; and forming a second conductor element overlying the second dielectric layer at a location overlying the first conductor element.

13 . The method of claim 12 , wherein the step of forming the first conductor element comprises:
depositing a first conductive layer over the first dielectric layer; and patterning the first conductive layer to define a first capacitor plate at the location overlying the first well region; and wherein the step of forming the second conductor element comprises:
depositing a second conductive layer over the second dielectric layer; and
patterning the second conductive layer to define a second capacitor plate at the location overlying the first capacitor plate.

14 . The method of claim 12 , wherein the step of forming the first conductor element comprises:
depositing a first conductive layer over the first dielectric layer; and patterning the first conductive layer to define a first inductor coil at the location overlying the first well region; and wherein the step of forming the second conductor element comprises:
depositing a second conductive layer over the second dielectric layer; and
patterning the second conductive layer to define a second inductor coil at the location overlying the first capacitor plate.

15 . The method of claim 12 , further comprising:
forming a first and second contact regions of the second conductivity type at the surface, the first contact region disposed at a location of the surface between the first and second well regions and in contact with the tank region, and the second contact region disposed at a location of the surface outside of the second well region relative to the tank region and in contact with the substrate.

16 . The method of claim 15 , further comprising:
forming a plurality of metal conductors overlying the surface, respective ones of the plurality of metal conductors in ohmic contact with the first contact region, the second contact region, the first well region, and the second well region.

17 . The method of claim 16 , further comprising:
forming a plurality of resistors near the surface, respective ones of the resistors in contact with respective ones of the plurality o

Assignees

• Texas Instruments Inc

Inventors

• Selvaraj Raja
• Kamath Anant Shankar
• Williams Byron Lovell
• Bonifield Thomas D
• Arch John Kenneth

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title