Semiconductor device and method of manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-2016293709-A1
Application number	US-201615076753-A
Country	US
Kind code	A1
Filing date	Mar 22, 2016
Priority date	Mar 31, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

Characteristics of a semiconductor device are improved. A semiconductor device includes a voltage clamp layer, a channel base layer, a channel layer, and a barrier layer on a substrate. A trench extends to a certain depth of the channel layer through the barrier layer. A gate electrode is disposed on a gate insulating film within the trench. A source electrode and a drain electrode are provided on the two respective sides of the gate electrode. A coupling within a through-hole that extends to the voltage clamp layer electrically couples the voltage clamp layer to the source electrode. An impurity region containing an impurity having an acceptor level deeper than that of a p-type impurity is provided under the through-hole. The voltage clamp layer decreases variations in characteristics such as threshold voltage and on resistance. The contact resistance is reduced through hopping conduction due to the impurity in the impurity region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a first nitride semiconductor layer provided over the substrate; a second nitride semiconductor layer provided over the first nitride semiconductor layer; a gate electrode disposed over the second nitride semiconductor layer; a first electrode and a second electrode provided over the second nitride semiconductor layer on two respective sides of the gate electrode; a coupling that couples the first electrode to the first nitride semiconductor layer; and an impurity region provided between the coupling and the first nitride semiconductor layer, wherein the first nitride semiconductor layer contains a p-type impurity, and wherein the impurity region contains an impurity having an acceptor level deeper than an acceptor level of the p-type impurity.

2 . The semiconductor device according to claim 1 , wherein the impurity having the deep acceptor level includes at least one of Zn, Cd, Be, and C.

3 . The semiconductor device according to claim 1 , wherein the impurity region is provided in an entire area of a surface portion of the first nitride semiconductor layer.

4 . The semiconductor device according to claim 1 , further comprising a third nitride semiconductor layer provided over the second nitride semiconductor layer.

5 . The semiconductor device according to claim 4 , wherein electron affinity of the third nitride semiconductor layer is smaller than electron affinity of the second nitride semiconductor layer.

6 . The semiconductor device according to claim 5 , further comprising a fourth nitride semiconductor layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer.

7 . The semiconductor device according to claim 6 , wherein electron affinity of the fourth nitride semiconductor layer is smaller than electron affinity of the second nitride semiconductor layer.

8 . The semiconductor device according to claim 1 , wherein the substrate has a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are provided in the first region, wherein the second region is a device isolation region provided in the second nitride semiconductor layer, and wherein the coupling is disposed in an inside of a through-hole that extends to the first nitride semiconductor layer through the device isolation region.

9 . The semiconductor device according to claim 8 , wherein a first terminal section to be electrically coupled to the first electrode is disposed over the coupling.

10 . The semiconductor device according to claim 8 , wherein a bottom of the through-hole is located on a surface of the impurity region or located at a certain depth of the impurity region.

11 . The semiconductor device according to claim 1 , wherein the substrate has a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are provided in the first region, wherein the second region is a device isolation region provided in the second nitride semiconductor layer, and wherein the coupling is disposed in an inside of a through-hole that extends to the first nitride semiconductor layer through the second nitride semiconductor layer.

12 . The semiconductor device according to claim 11 , wherein the first electrode is disposed over the coupling.

13 . The semiconductor device according to claim 4 , further comprising a trench that extends to a certain depth of the second nitride semiconductor layer through the third nitride semiconductor layer,
wherein the gate electrode is disposed within the trench through a gate insulating film.

14 . The semiconductor device according to claim 4 , further comprising a fifth nitride semiconductor layer over the third nitride semiconductor layer,
wherein the gate electrode is disposed over the third nitride semiconductor layer with the fifth nitride semiconductor layer in between, and wherein electron affinity of the fifth nitride semiconductor layer is larger than electron affinity of the third nitride semiconductor layer.

15 . A semiconductor device, comprising:
a substrate; a first nitride semiconductor layer provided over the substrate; a second nitride semiconductor layer provided over the first nitride semiconductor layer; a gate electrode disposed over the second nitride semiconductor layer; a first electrode and a second electrode provided over the second nitride semiconductor layer on two respective sides of the gate electrode; a coupling that couples the first electrode to the first nitride semiconductor layer; and a defect region provided between the coupling and the first nitride semiconductor layer, wherein the first nitride semiconductor layer contains a p-type impurity.

16 . A method of manufacturing a semiconductor device, the method comprising the steps of:
(a) forming a first nitride semiconductor layer containing a p-type impurity over a substrate; (b) forming a second nitride semiconductor layer over the first nitride semiconductor layer; (c) forming a gate electrode over the second nitride semiconductor layer; (d) forming a first electrode and a second electrode over the second nitride semiconductor layer on two respective sides of the gate electrode; (e) forming a through-hole that extends to the first nitride semiconductor layer through one of the second nitride semiconductor layer and a device isolation region provided in the second nitride semiconductor layer; (f) forming an impurity region under the through-hole; and (g) forming a coupling by filling an inside of the through-hole with a conductive film, wherein the coupling couples the first electrode to the first nitride semiconductor layer, and wherein, in the step (f), the impurity region is formed by implanting an impurity into a portion under the through-hole, the impurity having an acceptor level deeper than an acceptor level of the p-type impurity.

17 . The method according to claim 16 , wherein the impurity having the deep acceptor level includes at least one of Zn, Cd, Be, and C.

18 . A method of manufacturing a semiconductor device, the method comprising the steps of:
(a) forming a first nitride semiconductor layer containing a p-type impurity over a substrate while an impurity region is formed over an entire area of a surface portion of the first nitride semiconductor layer; (b) forming a second nitride semiconductor layer over the first nitride semiconductor layer; (c) forming a gate electrode over the second nitride semiconductor layer; (d) forming a first electrode and a second electrode over the second nitride semiconductor layer on two respective sides of the gate electrode; (e) forming a through-hole that extends to the impurity region through one of the second nitride semiconductor layer and a device isolation region provided in the second nitride semiconductor layer; and (f) forming a coupling by filling an inside of the through-hole with a conductive film, wherein the coupling couples the first electrode to the first nitride semiconductor layer, and wherein, in the step (a), after a first layer containing the p-type impurity is formed, the impurity region as a second layer containing the p-type impurity and an impurity having an acceptor level deeper than an acceptor level of the p-type impurity is formed over the first layer.

19 . The method according to claim 18 , wherein the impurity having the deep acceptor level includes at least one of Zn, Cd

Assignees

• Renesas Electronics Corp

Inventors

• Nakayama Tatsuo
• Miyamoto Hironobu

Classifications

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title