Driver using pull-up nmos transistor

Patent metadata

Field	Value
Publication number	US-2016285453-A1
Application number	US-201514957188-A
Country	US
Kind code	A1
Filing date	Dec 2, 2015
Priority date	Mar 25, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

In one embodiment, a system comprises a pre-driver circuit and a driver. The pre-driver circuit is powered by a first supply voltage, and configured to output a pre-drive signal. The driver comprises a pull-up NMOS transistor having a drain coupled to a second supply voltage, and a source coupled to an output of the driver, wherein the second supply voltage is lower than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor. The driver also comprises a drive circuit coupled to a gate of the pull-up NMOS transistor, wherein the drive circuit is configured to receive the pre-drive signal and to drive the gate of the pull-up NMOS transistor with a voltage approximately equal to the first supply voltage to drive the output of the driver to a high state depending on a logic state of the pre-drive signal.

First claim

1 . A system, comprising:
a pre-driver circuit powered by a first supply voltage, and configured to output a pre-drive signal; and a driver, the driver comprising:
a pull-up NMOS transistor having a drain coupled to a second supply voltage, and a source coupled to an output of the driver, wherein the second supply voltage is lower than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor; and
a drive circuit coupled to a gate of the pull-up NMOS transistor, wherein the drive circuit is configured to receive the pre-drive signal and to drive the gate of the pull-up NMOS transistor with a voltage approximately equal to the first supply voltage to drive the output of the driver to a high state depending on a logic state of the pre-drive signal.

2 . The system of claim 1 , wherein the drive circuit comprises an inverter having an input coupled to the pre-driver circuit and an output coupled to the gate of the pull-up NMOS transistor, wherein the inverter is powered by the first supply voltage.

3 . The system of claim 1 , wherein the driver further comprises a pull-down NMOS transistor having a drain coupled to the output of the driver, and a source coupled to a ground, wherein the drive circuit is coupled to a gate of the pull-down NMOS transistor and is configured to drive the gate of the pull-down NMOS transistor with a voltage approximately equal to the first supply voltage to drive the output of the driver to a low state depending on the logic state of the pre-drive signal.

4 . The system of claim 3 , wherein the drive circuit comprises:
an inverter having an input coupled to the pre-driver circuit and an output coupled to the gate of the pull-up NMOS transistor, wherein the inverter is powered by the first supply voltage; and a delay circuit having an input coupled to the pre-driver circuit and an output coupled to the gate of the pull-down NMOS transistor, wherein the delay circuit is powered by the first supply voltage.

5 . The system of claim 4 , wherein a delay of the delay circuit approximately equals a propagation delay of the inverter.

6 . The system of claim 1 , wherein the output of the driver has a voltage swing approximately equal to the second supply voltage.

7 . The system of claim 6 , wherein the pre-drive signal has a voltage swing approximately equal to the first supply voltage.

8 . The system of claim 1 , wherein the first supply voltage is a core voltage used to power a processing core on a chip on which the system is implemented.

9 . The system of claim 1 , wherein the pre-driver circuit comprises a latch configured to receive an input signal and a clock signal, to latch the input signal using the clock signal to generate an output signal, wherein the pre-drive signal is based on the output signal and the latch is powered by the first supply voltage.

10 . The system of claim 1 , wherein the system is implemented on a chip, and the first supply voltage and second supply voltage are provided by a power source external to the chip.

11 . A method for driving a driver, the driver comprising a pull-up NMOS transistor having a drain coupled to a first power supply and a source coupled to an output of the driver, the method comprising:
receiving a pre-drive signal from a pre-driver circuit powered by a second supply voltage, wherein the second supply voltage is higher than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor; and driving a gate of the pull-up NMOS transistor with a voltage approximately equal to the second supply voltage to drive the output of the driver to a high state depending on a logic state of the received pre-drive signal.

12 . The method of claim 11 , wherein the driver further comprises a pull-down NMOS transistor having a drain coupled to the output of the driver, and a source coupled to a ground, and wherein the method further comprises:
driving a gate of the pull-down NMOS transistor with a voltage approximately equal to the second supply voltage to drive the output of the driver to a low state depending on the logic state of the received pre-drive signal.

13 . The method of claim 11 , wherein the output of the driver has a voltage swing approximately equal to the first supply voltage.

14 . The method of claim 13 , wherein the pre-drive signal has a voltage swing approximately equal to the second supply voltage.

15 . The method of claim 11 , wherein the second supply voltage is a core voltage used to power a processing core on a chip on which the driver and pre-driver circuit are implemented.

16 . An apparatus for driving a driver, the driver comprising a pull-up NMOS transistor having a drain coupled to a first power supply and a source coupled to an output of the driver, the apparatus comprising:
means for receiving a pre-drive signal from a pre-driver circuit powered by a second supply voltage, wherein the second supply voltage is higher than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor; and means for driving a gate of the pull-up NMOS transistor with a voltage approximately equal to the second supply voltage to drive the output of the driver to a high state depending on a logic state of the received pre-drive signal.

17 . The apparatus of claim 16 , wherein the driver further comprises a pull-down NMOS transistor having a drain coupled to the output of the driver, and a source coupled to a ground, and wherein the apparatus further comprises:
means for driving a gate of the pull-down NMOS transistor with a voltage approximately equal to the second supply voltage to drive the output of the driver to a low state depending on the logic state of the received pre-drive signal.

18 . The apparatus of claim 16 , wherein the output of the driver has a voltage swing approximately equal to the first supply voltage.

19 . The apparatus of claim 18 , wherein the pre-drive signal has a voltage swing approximately equal to the second supply voltage.

20 . The apparatus of claim 16 , wherein the second supply voltage is a core voltage used to power a processing core on a chip on which the driver and pre-driver circuit are implemented.

Assignees

• Qualcomm Inc

Inventors

• Thilenius Stephen Clifford
• Isakanian Patrick
• Loke Alvin Leng Sun
• Bryan Thomas Clark
• Peterson Luverne Ray

Classifications

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K19/017518 Primary

  using a combination of bipolar and field effect transistors [BIFET] · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• H03K19/018507

  Interface arrangements · CPC title