Integrated differential clock gater

Patent metadata

Field	Value
Publication number	US-2016285437-A1
Application number	US-201514668183-A
Country	US
Kind code	A1
Filing date	Mar 25, 2015
Priority date	Mar 25, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A technique implements differential digital logic circuits with a differential clock distribution network using standard cell differential clock gater circuits to reduce area, delay, power consumption in integrated circuits. An apparatus includes a first terminal configured to receive a clock signal, a second terminal configured to receive a complementary clock signal, and a third terminal configured to receive a clock control signal. The apparatus includes a latch circuit configured to generate a latched version of the clock control signal based on a version of the clock control signal, a version of the clock signal, and a version of the complementary clock signal. The apparatus includes a combinatorial circuit configured to generate a gated clock signal and a gated complementary clock signal based on the version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal.

First claim

1 . An apparatus comprising:
a first terminal configured to receive a clock signal; a second terminal configured to receive a complementary clock signal; a third terminal configured to receive a clock control signal; a latch circuit configured to generate a latched version of the clock control signal based on a version of the clock control signal, a version of the clock signal, and a version of the complementary clock signal; and a combinatorial circuit configured to generate a gated clock signal and a gated complementary clock signal based on the latched version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal.

2 . The apparatus, as recited in claim 1 , wherein the latch circuit comprises:
a selective pass circuit configured to pass the version of the clock control signal based on the version of the clock signal and the version of the complementary clock signal.

3 . The apparatus, as recited in claim 2 , wherein the selective pass circuit comprises:
a transmission gate configured to pass an inverted version of the clock control signal in response to the version of the clock signal and the version of the complementary clock signal.

4 . The apparatus, as recited in claim 1 , wherein the clock control signal is a clock enable signal and in response to the clock control signal having a low level, the combinatorial circuit generates the gated clock signal having a low level and the gated complementary clock signal having a high level.

5 . The apparatus, as recited in claim 1 , wherein the clock signal and the complementary clock signal form a differential clock signal and the apparatus further comprises a current mode logic circuit coupled to the differential clock signal.

6 . The apparatus, as recited in claim 1 , wherein the latch circuit comprises:
a tri-state inverter configured to generate an inverted version of the clock control signal in response to the clock control signal, the version of the clock signal, and the version of the complementary clock signal.

7 . The apparatus, as recited in claim 1 , wherein the version of the clock signal and the version of the complementary clock signal are the same as the clock signal and the complementary clock signal, respectively.

8 . The apparatus, as recited in claim 1 , further comprising:
an edge-alignment circuit configured to generate the version of the clock signal and the version of the complementary clock signal based on the clock signal and the complementary clock signal, wherein opposite edges of the version of the clock signal and the version of the complementary clock signal are aligned.

9 . The apparatus, as recited in claim 8 , wherein the edge-alignment circuit comprises a pair of cross-coupled inverters.

10 . The apparatus, as recited in claim 1 , embodied in computer-readable descriptive form of a standard cell.

11 . A method comprising:
receiving a clock signal; receiving a complementary clock signal; receiving a clock control signal; selectively passing a version of the clock control signal according to a version of the clock signal and a version of the complementary clock signal; generating a latched version of the clock control signal based on the version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal; and generating a gated clock signal and a gated complementary clock signal based on the latched version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal.

12 . The method, as recited in claim 11 , wherein the clock control signal is a clock enable signal and in response to the clock control signal having a low level, the combinatorial circuit generates the gated clock signal having a low level and the gated complementary clock signal having a high level.

13 . The method, as recited in claim 11 , further comprising:
generating the version of the clock signal and the version of the complementary clock signal based on the clock signal and the complementary clock signal, wherein opposite edges of the version of the clock signal and the version of the complementary clock signal are aligned.

14 . The method, as recited in claim 11 , further comprising:
differentially controlling a digital logic circuit according to the version of the clock signal and the version of the complementary clock signal.

15 . The method, as recited in claim 11 , further comprising:
routing the gated clock signal and the gated complementary clock signal to generate a routed clock signal and a routed complementary clock signal; generating a gated version of the routed clock signal and a gated version of the routed complementary clock signal.

16 . An apparatus comprising:
a skew-correcting differential clock gating circuit; and a plurality of differential clock gating circuits cascaded in series, a first differential clock gating circuit of the plurality of differential clock gating circuits being coupled to the output of the skew correcting differential clock gating circuit.

17 . The apparatus, as recited in claim 16 , further comprising:
an additional skew-correcting differential clock gating circuit coupled to the output of a last differential clock gating circuit of the plurality of differential clock gating circuits.

18 . The apparatus, as recited in claim 16 , further comprising:
a current mode logic circuit coupled to the output of a last differential clock gating circuit of the plurality of differential clock gating circuits.

19 . The apparatus, as recited in claim 16 , wherein the skew-correcting differential clock gating circuit comprises:
a first terminal configured to receive a clock signal; a second terminal configured to receive a complementary clock signal; a third terminal configured to receive a clock control signal; an edge-alignment circuit configured to generate the version of the clock signal and the version of the complementary clock signal based on the clock signal and the complementary clock signal, wherein opposite edges of the version of the clock signal and the version of the complementary clock signal are aligned; a selective pass circuit configured to pass a version of the clock control signal based on a version of the clock signal and a version of the complementary clock signal; a latch circuit configured to generate a latched version of the clock control signal based on the clock control signal, the version of the clock signal, and the version of the complementary clock signal; and a combinatorial circuit configured to generate a gated clock signal and a gated complementary clock signal based on the version of the clock control signal, the latched version of the clock signal, and the version of the complementary clock signal.

20 . The apparatus, as recited in claim 16 , wherein the differential clock gating circuit comprises:
a first terminal configured to receive a clock signal; a second terminal configured to receive a complementary clock signal; a third terminal configured to receive a clock control signal; a selective pass circuit configured to pass an inverted version of the clock control signal based on a version of the clock signal and a version of the complementary clock signal; a latch circuit configured to generate a latched version of the clock control signal based on the inverted version of the clock control signal, the version of the clock signal, and the version of the complementary

Assignees

• Advanced Micro Devices Inc

Inventors

• Thazhatheppattu Hariprasad Thodukattil
• Vallur Prasant
• Sharma Animesh

Classifications

• H03K3/0372

  of the primary-secondary type · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• H03K3/037 Primary

  Bistable circuits · CPC title