Methods for fabricating anode shorted field stop insulated gate bipolar transistor

Patent metadata

Field	Value
Publication number	US-2016284797-A1
Application number	US-201615177191-A
Country	US
Kind code	A1
Filing date	Jun 8, 2016
Priority date	Jul 27, 2011
Publication date	Sep 29, 2016
Grant date	—

Abstract

A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

First claim

What is claimed is:

1 . A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising:
a) forming one or more insulated gate bipolar transistors (IGBT) component cells within a top surface of an epitaxial layer of a first conductivity type; b) thinning a back surface of the epitaxial layer to a desired thickness; c) performing a blanket implant of the first conductivity type to the back surface of the epitaxial layer to form a field stop layer, wherein a concentration of charge carriers in the field stop layer is greater than that of the epitaxial layer; d) selectively implanting first semiconductor regions of a second conductivity type that is opposite the first conductivity type within a back surface of the field stop layer using a first shadow mask, wherein a concentration of charge carriers in the first semiconductor regions is greater than that of the field stop layer; e) selectively implanting second semiconductor regions of the first conductivity type within a back surface of the field stop layer using a second shadow mask, wherein a concentration of charge carriers in the second semiconductor regions is greater than that of the field stop layer; and f) laser activating the first and second semiconductor regions; g) depositing a metal layer to a back surface of the first and second semiconductor regions.

2 . The method of claim 1 , wherein the epitaxial layer is doped n−, the field stop layer is doped n, the first semiconductor regions are doped p+ and the second semiconductor regions are doped n+.

3 . The method of claim 2 , wherein the first shadow mask and the second shadow mask are complementary.

4 . The method of claim 2 , wherein a width of the first implant regions of the second conductivity type is much larger than a width of second semiconductor regions of the first conductivity type.

5 . The method of claim 1 , wherein the blanket implant in c) is a Phosphorous implant with a concentration between 1×10 13 /cm 3 and 2×10 13 /cm 3 performed at 100-300 keV.

6 . A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising:
a) forming one or more insulated gate bipolar transistors (IGBT) component cells within a top surface of an epitaxial layer of a first conductivity type; b) thinning a back surface of the epitaxial layer to a desired thickness; c) performing a blanket implant of the first conductivity type to the back surface of the epitaxial layer to form a field stop layer, wherein a charge carrier concentration of the field stop layer is greater than that of the epitaxial layer; d) performing a blanket implant of a second conductivity type that is opposite the first conductivity type to a back surface of the field stop layer to form first semiconductor implant regions; e) laser activating the field stop layer and first semiconductor layer; f) depositing a first metal layer to a backside of the first semiconductor layer; g) selectively forming isolated semiconductor implant regions by laser cutting through one or more portions of the first metal layer and the first semiconductor implant region to expose one or more portions of the field stop layer; h) performing a blanket implant of the first conductivity type to the exposed portions of the field stop layer form second semiconductor implant regions within the exposed portions of the field stop layer, wherein a charge carrier concentration of the second semiconductor implant regions is greater than that of the field stop layer; i) depositing a second metal layer on the first metal layer and exposed portions of the second semiconductor implant regions.

7 . The method of claim 6 , wherein the epitaxial layer is doped n−, the field stop layer is doped n and the second semiconductor regions are doped n+.

8 . The method of claim 7 , wherein the first semiconductor layer is doped p+.

9 . The method of claim 8 , wherein the first metal layer makes good contact with the first semiconductor implant regions and the second metal layer makes good contact with the second semiconductor implant regions.

10 . A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising:
a) forming a semiconducting first epitaxial layer on a top surface of a semiconducting substrate, wherein the first epitaxial layer and substrate are of the same conductivity type and the first epitaxial layer has a lower concentration of charge carriers than the substrate; b) forming a semiconducting field stop layer on top of the first epitaxial layer, wherein the field stop layer is of the same conductivity type as the substrate and first epitaxial layer, wherein the field stop layer has a higher concentration of charge carriers than the first epitaxial layer and a lower concentration of charge carriers than the substrate; c) forming a semiconducting second epitaxial layer on top of the field stop layer, wherein the field stop layer is of the same conductivity type as the substrate, first epitaxial layer, and field stop layer, wherein the second epitaxial layer has a lower concentration of charge carriers than that of the substrate and field stop layer; d) forming one or more insulated gate bipolar transistors (IGBT) component cells in the second epitaxial layer; e) thinning the substrate to a desired thickness by removing material from a back side of the substrate; f) forming a metal pattern on a back surface of the substrate; g) performing an anisotropic etch on the back side of the substrate using the metal pattern as a mask, wherein the anisotropic etch exposes one or more portions of the first epitaxial layer; h) performing a backside blanket implant of dopants into the exposed portions of the first epitaxial layer to form implant regions, wherein the implant regions are of an opposite conductivity type to that of the substrate, first epitaxial layer, field stop layer, and second epitaxial layer; i) forming a metal layer on the back surface of the first semiconductor regions the metal pattern.

11 . The method of claim 10 , wherein the substrate is doped n+ type, the first epitaxial layer is doped n− type, the field stop layer is doped is n type.

12 . The method of claim 11 , wherein the second epitaxial layer is doped n− type

13 . The method of claim 11 , wherein the implant regions are doped p+ type.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bhalla Anup
• Bobde Madhur
• Ding Yongping
• Zhang Xiaotian
• Ho Yueh-Se

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title