Method of forming epitaxial buffer layer for finfet source and drain junction leakage reduction

Patent metadata

Field	Value
Publication number	US-2016284701-A1
Application number	US-201615170299-A
Country	US
Kind code	A1
Filing date	Jun 1, 2016
Priority date	May 1, 2014
Publication date	Sep 29, 2016
Grant date	—

Abstract

A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a gate structure on the channel region portion of a fin structure; at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure, wherein at least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion, wherein the second concentration portion has a greater dopant concentration than the first concentration doped portion; and an extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

2 . The semiconductor device of claim 1 , wherein the fin structure is comprised of silicon.

3 . The semiconductor device of claim 1 , wherein the epitaxial source region and the epitaxial drain region are comprised of silicon germanium.

4 . The semiconductor device of claim 3 , wherein the epitaxial source region and the epitaxial drain region are comprised on an n-type or p-type dopant.

5 . The semiconductor device of claim 3 , wherein the first concentration region has an L-shaped geometry with a vertical portion on a sidewall of the source region portion or drain region portion of the fin structure and a horizontal portion at a base of the epitaxial source region or epitaxial drain region.

6 . The semiconductor device of claim 3 , wherein a dopant concentration of n-type or p-type dopant in the first concentration doped portion of the epitaxial source region and the epitaxial drain region ranges from 1×10 15 atoms/cm 3 to 5×10 15 atoms/cm 3 .

7 . The semiconductor device of claim 3 , wherein a dopant concentration of n-type or p-type dopant in the second concentration doped portion of the epitaxial source region and the epitaxial drain region ranges from 5×10 20 atoms/cm 3 to 8×10 20 atoms/cm 3 .

8 . The semiconductor device of claim 3 , wherein the epitaxial source region and the epitaxial drain region are merge regions extending from the fin structure to an adjacent fin structure.

9 . A semiconductor device comprising:
at least one of a source region and a drain region on a source region portion and a drain region portion of the fin structure, wherein at least one of the source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion, wherein the second concentration portion has a greater dopant concentration than the first concentration doped portion; and an extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

10 . The semiconductor device of claim 9 , wherein the fin structure is comprised of silicon.

11 . The semiconductor device of claim 9 , wherein the source region and the drain region are comprised of silicon germanium.

12 . The semiconductor device of claim 11 , wherein the source region and the drain region are comprised on an n-type or p-type dopant.

13 . The semiconductor device of claim 11 , wherein the first concentration region has an L-shaped geometry with a vertical portion on a sidewall of the source region portion or drain region portion of the fin structure and a horizontal portion at a base of the source region or drain region.

14 . The semiconductor device of claim 11 , wherein a dopant concentration of n-type or p-type dopant in the first concentration doped portion of the source region and the drain region ranges from 1×10 15 atoms/cm 3 to 5×10 15 atoms/cm 3 .

15 . The semiconductor device of claim 11 , wherein a dopant concentration of n-type or p-type dopant in the second concentration doped portion of the source region and the drain region ranges from 5×10 20 atoms/cm 3 to 8×10 20 atoms/cm 3 .

16 . The semiconductor device of claim 11 , wherein the source region and the drain region are merge regions extending from the fin structure to an adjacent fin structure.

17 . A semiconductor device comprising:
at least one of a source region and a drain region on a source region portion and a drain region portion of the fin structure, wherein at least one of the source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion, the second concentration portion having a greater dopant concentration than the first concentration doped portion, wherein the first concentration region has an L-shaped geometry with a vertical portion on a sidewall of the source region portion or drain region portion of the fin structure and a horizontal portion at a base of the source region or drain region; and an extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

18 . The semiconductor device of claim 17 , wherein the fin structure is comprised of silicon.

19 . The semiconductor device of claim 17 , wherein the source region and the drain region are comprised of silicon germanium.

20 . The semiconductor device of claim 11 , wherein the source region and the drain region are merge regions extending from the fin structure to an adjacent fin structure.

Assignees

• IBM
• Renesas Electronics Corp

Inventors

• Guo Dechao
• Mochizuki Shogo
• Scholze Andreas
• Yeh Chun-Chen

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1404

  using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase · CPC title

• H10P32/171

  being group IV material · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/82

  Heterojunctions · CPC title