Utilizing a processor with a time of day clock error

Patent metadata

Field	Value
Publication number	US-2016283333-A1
Application number	US-201514667849-A
Country	US
Kind code	A1
Filing date	Mar 25, 2015
Priority date	Mar 25, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

Aspects of the present invention disclose a method for core utilization. The method includes identifying a faulty clock in a core of a plurality of cores. The method further includes initiating a recovery procedure of the faulty clock in the affected core. The method further includes determining that the recovery of the faulty clock was not successful. The method further includes adjusting the functionality of the core with the faulty clock.

First claim

What is claimed is:

1 . A method for core utilization, based on core clocks, the method comprising:
identifying, by one or more processors, a faulty clock, in a core of a plurality of cores in a multi-core computing system; initiating, by one or more processors, a recovery procedure for the faulty clock in the core of the plurality of cores; determining, by one or more processors, that the faulty clock, in the core of the plurality of cores, was not recovered; and adjusting, by one or more processors, functionality of the core, of the plurality of cores, with the faulty clock.

2 . The method of claim 1 , wherein the step of identifying, by one or more processors, a faulty clock, in a core of a plurality of cores, in a multi-core computing system comprises:
determining that all clocks in the multi-core computing system are not synchronized; and verifying that a system clock in the multi-core computing system is functioning correctly.

3 . The method of claim 2 , wherein the faulty clock, in the core of the plurality of cores, is not synchronized with the system clock.

4 . The method of claim 2 , wherein the step of verifying that the system clock in the multi-core computing system is functioning correctly comprises:
executing an internal check to verify integrity of a time of day value as seen by each core in the multi-core computing system.

5 . The method of claim 1 , wherein the recovery procedure includes one of the following: a redundant clock topology; a redundant oscillator; and a redundant master clock.

6 . The method of claim 2 , wherein the step of determining by one or more processors, that the faulty clock, in the core of the plurality of cores, was not recovered comprises:
checking whether the faulty clock is synchronized with the system clock.

7 . The method of claim 1 , wherein the step of adjusting, by one or more processors, the functionality of the core, of the plurality of cores, with the faulty clock comprises:
assigning to the core with the faulty clock, non-clock dependent operations.

8 . The method of claim 7 , wherein the non-clock dependent operations do not require an accurate clock reference to function properly and do not interact with other cores in the multi-processor computing system.

9 - 20 . (canceled)

Assignees

• IBM

Inventors

• Gupta Sachin
• Jha Prem S
• Sainath Venkatesh

Classifications

• G06F11/1679

  at clock signal level · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F11/1604 Primary

  where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware · CPC title

• G06F1/14

  Time supervision arrangements, e.g. real time clock · CPC title