Floating-point supportive pipeline for emulated shared memory architectures

Patent metadata

Field	Value
Publication number	US-2016283249-A1
Application number	US-201415031285-A
Country	US
Kind code	A1
Filing date	Oct 23, 2014
Priority date	Oct 23, 2013
Publication date	Sep 29, 2016
Grant date	—

Abstract

A processor architecture arrangement for emulated shared memory (ESM) architectures, comprising a number of multi-threaded processors each provided with interleaved inter-thread pipeline ( 400 ) and a plurality of functional units ( 402, 402 b, 402 c, 404, 404 b, 404 c ) for carrying out arithmetic and logical operations on data, wherein the pipeline ( 400 ) comprises at least two operatively parallel pipeline branches ( 414, 416 ), first pipeline branch ( 414 ) comprising a first sub-group of said plurality of functional units ( 402, 402 b, 402 c ), such as ALUs (arithmetic logic unit), arranged for carrying out integer operations, and second pipeline branch ( 416 ) comprising a second, non-overlapping sub-group of said plurality of functional units ( 404, 404 b, 404 c ), such as FPUs (floating point unit), arranged for carrying out floating point operations, and further wherein one or more of the functional units ( 404 b) of at least said second sub-group arranged for floating point operations are located operatively in parallel with the memory access segment ( 412, 412 a ) of the pipeline ( 400 ).

First claim

1 . A processor architecture arrangement for emulated shared memory (ESM) architectures, comprising;
a number of multi-threaded processors each provided with a interleaved inter-thread pipeline and a plurality of functional units for carrying out arithmetic and logical operations on data, wherein the interleaved inter-thread pipeline includes at least two operatively parallel pipeline branches a first pipeline branch having a first sub-group of said plurality of functional units which are arranged for carrying out integer operations, and a second pipeline branch having a second, non-overlapping, sub-group of said plurality of functional units arranged for carrying out floating point operations, and wherein at least one of the functional units of the second sub-group which is arranged for floating point operations is located operatively in parallel with a memory access segment of the pipeline.

2 . The processor architecture arrangement according to claim 1 , wherein at least one of the functional units of the first sub-group is located operatively in parallel with the memory access segment of the pipeline.

3 . The processor architecture arrangement according to claim 1 , wherein at least two or more of the functional units of the second sub-group in the second branch are chained together, and wherein a chained functional unit may pass an operation result to a subsequent functional unit in the chain as an operand.

4 . The processor architecture arrangement according to claim 1 , wherein a number of functional units in said first and/or second branch are functionally positioned before a memory, where some functional units are in parallel, and some functional units are after the memory access segment.

5 . The processor architecture arrangement according to claim 1 , wherein at least two functional units of the second sub-group are mutually of different complexity in terms operation execution latency.

6 . The processor architecture arrangement of claim 5 , wherein a functional unit associated with longer latency is logically located in parallel with an end portion of the memory access segment.

7 . The processor architecture arrangement according to claim 1 , wherein at least one functional unit is controllable through a number of operation selection fields of instruction words.

8 . The processor architecture arrangement according to claim 1 , wherein a number of operands for a functional unit can be determined in an operand select stage of the pipeline in accordance with a number of operand selection fields given in an instruction word.

9 . The processor architecture arrangement according to claim 1 , wherein the second sub-group of functional units in said second branch includes at least one functional unit configured to execute at least one floating-point operation selected from the group consisting of: addition, subtraction, multiplication, division, comparison, transformation from integer to floating point, transformation from floating point to integer, square root, logarithm, and exponentiation.

10 . The processor architecture arrangement according to claim 1 , wherein a first functional unit of said second sub-group is configured to execute a plurality of floating point operations and a second functional unit of said second sub-group is configured to execute one or more other floating point operations.

Assignees

• Teknologian Tutkimuskeskus Vtt Oy

Inventors

• Forsell Martti

Classifications

• G06F9/3875 Primary

  Pipelining a single stage, e.g. superpipelining · CPC title

• G06F9/3889

  controlled by multiple instructions, e.g. MIMD, decoupled access or execute · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F9/3893

  controlled in tandem, e.g. multiplier-accumulator · CPC title

• G06F9/3873

  Variable length pipelines, e.g. elastic pipeline · CPC title