Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gathering

Patent metadata

Field	Value
Publication number	US-9747101-B2
Application number	US-201113977729-A
Country	US
Kind code	B2
Filing date	Sep 26, 2011
Priority date	Sep 26, 2011
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.

First claim

What is claimed is:

1. A processor comprising:
a first register to comprise a first plurality of data fields, wherein each of the first plurality of data fields in the first register is to correspond to an offset for a data element in a memory, wherein for each of the first plurality of data fields in the first register, a first value is to indicate that the corresponding data element has not yet been gathered from the memory and a second value is to indicate that the corresponding data element does not need to be gathered, or has already been gathered from the memory;
a decode stage to decode a first instruction specifying a gather operation and specifying a second operation; and
one or more execution units, responsive to the decoded first instruction, to:
duplicate the first plurality of data fields in the first register;
read the values of each of the first plurality of data fields in the first register;
for each data field of the first plurality of data fields in the first register which is to have the first value, gather the corresponding data element from the memory and store the corresponding data element into a second register, the second register to have a second plurality of data fields, a portion of which to store gathered data elements, and change the data field in the first register from the first value to the second value; and
when each data field of the first plurality of data fields in the first register has the second value, perform the second operation using each of the gathered data elements that are to be stored in the second plurality of data fields to generate corresponding result data elements.

2. The processor of claim 1 , wherein the first value is one.

3. The processor of claim 1 , wherein the second value is zero.

4. The processor of claim 1 , wherein said one or more execution units, responsive to the decoded first instruction, are to use the duplicate of the first plurality of data fields in the first register when the second operation is performed.

5. The processor of claim 1 , wherein said one or more execution units, responsive to the decoded first instruction, are to duplicate each of the first plurality of data fields having the first value in the first register when the value of that data field in the first register is changed from the first value to the second value.

6. The processor of claim 1 , wherein the second operation is unary.

7. The processor of claim 1 , wherein the second operation is binary.

8. The processor of claim 1 , wherein the data elements that are to be stored into the second register are to be 32-bit data elements.

9. The processor of claim 1 , wherein the data elements that are to be stored into the second register are to be 64-bit data elements.

10. The processor of claim 1 , wherein the second register is a 512-bit vector register.

11. A non-transitory machine-readable medium to record functional descriptive material including a first executable instruction, which if executed by a machine, is to cause the machine to:
duplicate a first plurality of data fields in a first register;
read values of each data field of the first plurality of data fields in the first register, wherein each of the first plurality of data fields in the first register is to correspond to an offset for a data element in a memory, and wherein for each data field of the first plurality of data fields in the first register, a first value is to indicate that the corresponding data element has not been gathered from the memory and a second value is to indicate that the corresponding data element does not need to be gathered, or has already been gathered from the memory;
for each data field of the first plurality of data fields in the first register that is to have the first value, gather the corresponding data element from the memory and store the corresponding data element into a second register, the second register to have a second plurality of data fields, a portion of which to store gathered data elements, and change the data field in the first register from the first value to the second value; and then
when each data field of the first plurality of data fields in the first register has the second value, perform a second operation using each of the gathered data elements that are to be stored in the second plurality of data fields to generate corresponding result data elements.

12. The non-transitory machine-readable medium of claim 11 , wherein the first executable instruction, if executed by the machine, further causes the machine to:
use the duplicate of the first plurality of data fields in the first register when the second operation is performed.

13. The non-transitory machine-readable medium of claim 11 , wherein the first executable instruction, if executed by the machine, further causes the machine to:
duplicate each of the first plurality of data fields having the first value in the first register when the value of that data field in the first register is changed from the first value to the second value.

14. The non-transitory machine-readable medium of claim 11 , wherein the second operation is unary.

15. The non-transitory machine-readable medium of claim 11 , wherein the second operation is binary.

16. The non-transitory machine-readable medium of claim 11 , wherein the data elements to be stored into the second register are to be 32-bit data elements.

17. The non-transitory machine-readable medium of claim 11 , wherein the data elements to be stored into the second register are to be 64-bit data elements.

18. The non-transitory machine-readable medium of claim 11 , wherein the second register is a 512-bit vector register.

19. A processor comprising:
a decode stage to decode a first single-instruction multiple-data (SIMD) instruction that is to specify: a gather operation and a second operation, a destination register, an operand register, a memory address, and an indices register; and
one or more execution units, responsive to the decoded first SIMD instruction, to:
duplicate a first plurality of data fields in a mask register;
read values of each data field of the first plurality of data fields in the mask register, wherein each of the first plurality of data fields in the mask register is to correspond to an offset index in the indices register, for a corresponding data element offset in a memory from the memory address, and wherein for each data field of the first plurality of data fields in the mask register, a first value is to indicate that a corresponding data element has not been gathered from the memory and a second value is to indicate that the corresponding data element does not need to be gathered, or has already been gathered from the memory;
for each data field of the first plurality of data fields in the mask register that is to have the first value, gather the corresponding data element from the memory and store the corresponding data element into a data field in the destination register corresponding to the offset index in the indices register, and change the data field in the mask register from the first value to the second value; and
when each data field of the first plurality of data fields in the mask register has the second value, perform the second operation using stored data elements in the destination register and corresponding data elements in the operand register to generate corresponding result data elements.

20. The processor of claim 19 , wherein said one or more execution units, responsive to the decoded first SIMD instruction

Assignees

• Ould-Ahmed-Vall Elmoustapha
• Doshi Kshitij A
• Yount Charles R
• Sair Suleyman
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Doshi Kshitij A
• Yount Charles R
• Sair Suleyman

Classifications

• G06F15/8061

  Details on data memory access · CPC title

• G06F9/30105

  Register structure · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title