Apparatus and method for controlling the number of vector elements written to a data store while performing speculative vector write operations

Patent metadata

Field	Value
Publication number	US-9483438-B2
Application number	US-201414462194-A
Country	US
Kind code	B2
Filing date	Aug 18, 2014
Priority date	Oct 9, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A data processing apparatus and method for performing speculative vector access operations are provided. The data processing apparatus has a reconfigurable buffer accessible to vector data access circuitry and comprising a storage array for storing up to M vectors of N vectors elements. The vector data access circuitry performs speculative data write operations in order to cause vector elements from selected vector operands in a vector register bank to be stored into the reconfigurable buffer. On occurrence of a commit condition, the vector elements currently stored in the reconfigurable buffer are then written to a data store. Speculation control circuitry maintains a speculation width indication indicating the number of vector elements of each selected vector operand stored in the reconfigurable buffer. The speculation width indication is initialized to an initial value, but on detection of an overflow condition within the reconfigurable buffer the speculation width indication is modified to reduce the number of vector elements of each selected vector operand stored in the reconfigurable buffer. The reconfigurable buffer then responds to a change in the speculation width indication by reconfiguring the storage array to increase the number of vectors M and reduce the number of vector elements N per vector. This provides an efficient mechanism for supporting performance of speculative data write operations.

First claim

We claim:

1. A data processing apparatus comprising:
a vector register bank configured to store vector operands for access by processing circuitry, each vector operand comprising a plurality of vector elements;
vector data access circuitry for performing vector access operations in order to move vector operands between the vector register bank and a data store;
a reconfigurable buffer accessible to the vector data access circuitry and comprising a storage array for storing up to M vectors of N vector elements, where the values of M and N are reconfigurable;
the vector data access circuitry being configured to perform speculative data write operations in order to cause vector elements from selected vector operands in the vector register bank to be stored into said reconfigurable buffer, on occurrence of a commit condition, the vector data access circuitry further being configured to cause the vector elements currently stored in the reconfigurable buffer to be written to the data store;
speculation control circuitry configured to maintain a speculation width indication indicating the number of vector elements of each selected vector operand stored in the reconfigurable buffer, the speculation width indication being initialised to an initial value, and on detection of an overflow condition within the reconfigurable buffer the speculation width indication being modified to reduce the number of vector elements of each selected vector operand stored in the reconfigurable buffer; and
the reconfigurable buffer being responsive to a change in the speculation width indication to reconfigure the storage array to increase the number of vectors M and reduce the number of vector elements N per vector.

2. A data processing apparatus as claimed in claim 1 , wherein the speculation control circuitry is responsive to execution of a start speculation instruction to trigger a speculative mode of operation during which the vector data access circuitry is configured to perform said speculative data write operations.

3. A data processing apparatus as claimed in claim 1 , wherein the speculation control circuitry is responsive to execution of a commit instruction to indicate the occurrence of the commit condition to the vector data access circuitry and to terminate speculation.

4. A data processing apparatus as claimed in claim 3 , wherein the speculation control circuitry is responsive to execution of one of said start speculation instruction and said commit instruction to initialise the speculation width indication to said initial value.

5. A data processing apparatus as claimed in claim 1 , wherein if the speculation control circuitry is responsive to the overflow condition to modify the speculation width indication to indicate that only one vector element of each selected vector operand is to be stored in the reconfigurable buffer, the speculation control circuitry is configured to cause the vector data access circuitry to write to the data store the first vector element of each vector currently stored in the reconfigurable buffer.

6. A data processing apparatus as claimed in claim 5 , wherein if the speculation control circuitry is responsive to the overflow condition to modify the speculation width indication to indicate that only one vector element of each vector operand is to be stored in the reconfigurable buffer, the speculation control circuitry is configured to terminate speculation.

7. A data processing apparatus as claimed in claim 6 , wherein the vector data access circuitry is responsive to subsequent data write operations arising prior to occurrence of the commit condition to cause the first vector element of the selected vector operands to be written to the data store rather than into the reconfigurable buffer.

8. A data processing apparatus as claimed in claim 1 , wherein for each speculative data write operation the first vector element of each selected vector operand is written to the data store rather than to the reconfigurable buffer, and any remaining vector elements indicated by the speculation width indication are stored into the reconfigurable buffer.

9. A data processing apparatus as claimed in claim 1 , wherein each time the overflow condition is detected the speculation control circuitry is configured to modify the speculation width indication in order to reduce the number of vector elements N per vector by a factor of two.

10. A data processing apparatus as claimed in claim 1 , wherein the reconfigurable buffer is arranged, on reconfiguring the storage array in response to a modified speculation width indication, to discard any vector elements in the reconfigurable buffer that lie outside the number of vector elements indicated by the modified speculation width.

11. A data processing apparatus as claimed in claim 1 , wherein:
the vector data access circuitry is further configured to perform speculative data read operations in order to cause vector elements of selected vector operands to be read from said data store for storage in said vector register bank, the number of vector elements of each selected vector operand being dependent on said speculation width indication.

12. A data processing apparatus as claimed in claim 11 , wherein:
the reconfigurable buffer is configured to store, for each speculative data write operation performed, the vector elements forming a write vector to be written and address indication data used to determine an address of each of said vector elements of the write vector, the reconfigurable buffer further being configured to store, for each speculative data read operation, address indication data used to identify an address for each vector element forming a read vector to be read by that speculative data read operation.

13. A data processing apparatus as claimed in claim 12 , wherein each write vector and each read vector comprise element positions from an initial start position K to a position X, where K and X are dependent on the speculation width indication, the apparatus further comprising:
address comparison circuitry configured to determine whether an address of a first vector element associated with a current speculative data access operation matches an address of a second vector element associated with address indication data stored in the reconfigurable buffer;
in the event of said match being determined, and if at least one of the first vector element and the second vector element forms part of a write vector, and the second vector element is at a higher element position than the first vector element, the speculation control circuitry is configured to modify the speculation width indication to reduce the number of vector elements in each write vector and each read vector.

14. A data processing apparatus as claimed in claim 13 , wherein if the second vector element is at element position j between element positions K and X, the speculation control circuitry is configured to modify the speculation width indication to reduce the number of vector elements in each write vector and each read vector to include vector element positions K to j-1.

15. A data processing apparatus as claimed in claim 13 , wherein in the event of the address comparison circuitry determining that the address of a first vector element within a current speculative data access operation matches the address of multiple second vector elements associated with address indication data stored in the reconfigurable buffer, the address comparison circuitry is configured to determine as a matching second vector element the second vector element amongst said multiple second vector elements having the lowest element positi

Assignees

• Advanced Risc Mach Ltd

Inventors

• Reid Alastair David
• Kershaw Daniel

Classifications

• G06F9/3875

  Pipelining a single stage, e.g. superpipelining · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title