Verification of gate driver protection logic

Patent metadata

Field	Value
Publication number	US-2016282407-A1
Application number	US-201514665927-A
Country	US
Kind code	A1
Filing date	Mar 23, 2015
Priority date	Mar 23, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A gate driver is described that includes a gate signal module configured to output a gate signal of the gate driver for driving a gate terminal of a semiconductor device. The gate driver further includes a test module configured to generate a simulated failure condition at a semiconductor device during a test of a monitoring and protection feature of the gate driver. The gate drier further includes a monitor module configured to output an indication of the simulated failure condition in response to detecting the simulated failure condition at the semiconductor device.

First claim

What is claimed is:

1 . A gate driver comprising:
a gate signal module configured to output a gate signal of the gate driver for driving a gate terminal of a semiconductor device; a test module configured to generate a simulated failure condition at a semiconductor device during a test of a monitoring and protection feature of the gate driver; and a monitor module configured to output an indication of the simulated failure condition in response to detecting the simulated failure condition at the semiconductor device.

2 . The gate driver of claim 1 , further comprising:
a blanking counter configured to delay the outputting of the indication of the simulated failure condition for at least a transition phase of a gate control signal received by the gate signal module from a control module.

3 . The gate driver of claim 1 , wherein the monitor module is a desaturation type monitoring and protection feature of the gate driver and is further configured to output an indication of a desaturation condition associated with the semiconductor device that the monitor module detects at a desaturation pin of the gate driver.

4 . The gate driver of claim 3 , further comprising a switch, wherein the test module is configured to generate the simulated failure condition by at least:
closing the switch to clamp the desaturation pin of the gate driver to ground level during a blanking period of the test of the monitoring and protection feature of the gate driver; and opening the switch after the blanking period of the test of the monitoring and protection feature of the gate driver.

5 . The gate driver of claim 4 , wherein the monitor module comprises a pull-up resistor coupled to the desaturation pin of the gate driver and configured to increase a voltage at the desaturation pin from ground to a voltage threshold after the test module opens the switch after the blanking period of the test of the monitoring and protection feature of the gate driver.

6 . The gate driver of claim 3 , wherein the test module is further configured to generate the simulated failure condition by at least inhibiting the gate driver from outputting a gate signal to the semiconductor device during the test of the monitoring and protection feature of the gate driver.

7 . The gate driver of claim 1 , wherein the monitor module is an overcurrent type monitoring and protection feature of the gate driver and is further configured to output an indication of an overcurrent condition associated with the semiconductor device that the monitor module detects at an overcurrent protection pin of the gate driver.

8 . The gate driver of claim 7 , further comprising a switch, wherein the test module is configured to generate the simulated failure condition by at least:
generating a weak on or off gate signal for output to the semiconductor device during the test of the monitoring and protection feature of the gate driver, wherein the weak on or off gate signal has less current than a nominal gate signal that holds the semiconductor device in an on-state or off-state at times other than during the test; opening the switch before and during a blanking period of the test of the monitoring and protection feature of the gate driver to maintain the overcurrent protection pin of the gate driver at a ground level; closing the switch to clamp the overcurrent protection pin of the gate driver to a voltage threshold after the blanking period of the test of the monitoring and protection feature.

9 . The gate driver of claim 8 , wherein the test module comprises a pull-up resistor coupled to VCC, wherein closing the switch to clamp the overcurrent protection pin of the gate driver to the voltage threshold after the blanking period of the test of the monitoring and protection feature comprises coupling the overcurrent protection pin to the pull-up resistor via the switch.

10 . The gate driver of claim 1 , wherein the semiconductor device is a power switch comprising at least one metal-oxide-semiconductor field-effect-transistor device or insulated-gate bipolar transistor device.

11 . The gate driver of claim 1 , wherein the monitor module is further configured to output an indication of an actual failure condition not attributed to the test module in response to detecting the actual failure condition at the semiconductor device.

12 . The gate driver of claim 1 , wherein the gate signal module is further configured to output the gate signal based on a control signal received by the gate driver from a control unit.

13 . A method for testing of a monitoring and protection feature of a gate driver, the method comprising:
initiating, by a control module, a test of the monitoring and protection feature of the gate driver during which the gate driver simulates a failure condition associated with a semiconductor device; responsive to receiving an indication of an error being output by the gate driver in response to the simulated failure condition, measuring, by the control module, an amount of time for the gate driver to output the indication of the error after initiating the test; comparing, by the control module, the measured amount of time to an expected time threshold; and responsive to determining the measured amount of time does not satisfy the expected time threshold, determining that a failure of the monitoring and protection feature of the gate driver occurred.

14 . The method of claim 13 , wherein the expected time threshold is based at least in part on a blanking period associated with the gate driver that prevents anomalies detected during the test from being output by the gate driver.

15 . The method of claim 14 , further comprising:
outputting, by the control module, to the gate driver, a gate control signal, wherein the blanking period occurs after a transition phase of the gate control signal.

16 . The method of claim 13 , wherein the monitoring and protection feature of the gate driver comprises an overcurrent type monitoring and protection feature of the gate driver.

17 . The method of claim 16 , wherein the expected time threshold is based at least in part on a rise time associated with a voltage level at an overcurrent protection pin of the gate driver, the rise time being an expected amount of time for the voltage level to increase from ground level to a voltage threshold due to a pull-up resistor associated with the gate driver after the overcurrent protection pin is pulled to the voltage threshold after initiation of the test.

18 . The method of claim 13 , wherein the monitoring and protection feature of the gate driver comprises a desaturation type monitoring and protection feature of the gate driver.

19 . The method of claim 18 , wherein the expected time threshold is based at least in part on a rise time associated with a voltage level at a desaturation pin of the gate driver, the rise time being an expected amount of time for the voltage level to increase from ground level to a voltage threshold due to a pull-up resistor associated with the gate driver after the desaturation pin is pulled to ground following initiation of the test.

20 . A computer-readable storage medium comprising instructions that, when executed, configure at least one processor of a control module to test a monitoring and protection feature of a gate driver by at least:
initiating a test of the monitoring and protection feature of the gate driver during which the gate driver simulates a failure condition associated with a semiconductor device; responsive to

Assignees

• Infineon Technologies Ag

Inventors

• Bacigalupo Tommaso
• Bachhuber Marco
• Nuebling Marcus
• Beaurenaut Laurent

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• G05F1/00

  Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems · CPC title

• G01R31/3187

  Built-in tests · CPC title

• G01R31/00

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title