Snubber circuit

Patent metadata

Field	Value
Publication number	US-2016277017-A1
Application number	US-201615166236-A
Country	US
Kind code	A1
Filing date	May 26, 2016
Priority date	Sep 13, 2011
Publication date	Sep 22, 2016
Grant date	—

Abstract

A snubber circuit is provided. The snubber circuit includes a transistor structure and a first capacitor. The transistor structure includes a chip package and two pins. The chip package includes a transistor die and a molding compound encapsulating the transistor die. A first pin of the two pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin of the two pins is electrically connected to a third bonding pad of the transistor die. The first pin or the second pin of the transistor structure is electrically connected to a terminal of the first capacitor.

First claim

What is claimed is:

1 . A snubber circuit, comprising:
a transistor structure, comprising:
a chip package, comprising a transistor die and a molding compound encapsulating the transistor die; and
two pins, wherein a first pin is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and a second pin is electrically connected to a third bonding pad of the transistor die; and
a first capacitor, wherein the first pin or the second pin of the transistor structure is electrically connected to a terminal of the first capacitor.

2 . The snubber circuit of claim 1 , wherein the snubber circuit is connected to an active component or a load in parallel; and the snubber circuit absorbs spikes or noise generated by the active component or the load to the first capacitor, and transmits energy of the absorbed spikes or the absorbed noise from the first capacitor to the active component or the load.

3 . The transistor structure of claim 2 , wherein the active component is or is assembled by a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a Static Induction Transistor (SIT), or a thyristor; and the load is or is assembled by an inductor, a resistor, or a second capacitor.

4 . The snubber circuit of claim 1 , wherein the first bonding pad and the second bonding pad are directly connected.

5 . The snubber circuit of claim 1 , wherein the transistor die is a Bipolar Junction Transistor (BJT) die.

6 . The snubber circuit of claim 5 , wherein the first bonding pad of the transistor die is an emitter bonding pad, the second bonding pad is a base bonding pad, and the third bonding pad is a collector bonding pad.

7 . The snubber circuit of claim 5 , wherein the snubber circuit is connected to an active component or a load in parallel; and the snubber circuit uses a characteristic of fast turning on and a characteristic of long storage time of the BJT die to absorb spikes or noise generated by the active component or the load to the first capacitor, and transmit energy of the absorbed spikes or the absorbed noise from the first capacitor to the active component or the load.

8 . The snubber circuit of claim 1 , further comprising:
a zener diode, wherein the terminal of the first capacitor is further connected to a terminal of a zener diode, and another terminal of the first capacitor is connected to another terminal of the zener diode.

9 . The snubber circuit of claim 1 , further comprising:
a resistor, coupled to the first capacitor in series, wherein one of the resistor and the first capacitor is connected between the first pin or the second pin of the transistor structure and the other of the resistor and the first capacitor.

10 . The snubber circuit of claim 1 , wherein the first bonding pad, the second bonding pad, and the third bonding pad are connected to the two pins through wire bonding.

11 . The snubber circuit of claim 10 , wherein the wire bonding includes three bonding wires connected to the two pins respectively.

12 . The snubber circuit of claim 10 , wherein the first bonding pad and the second bonding pad are electrically connected to each other, one of the first pin and the second pin is connected to the first bonding pad or the second bonding pad through a first bonding wire, and the third bonding pad is connected to another of the first pin and the second pin through a second bonding wire.

13 . The snubber circuit of claim 10 , wherein the first bonding pad is electrically connected to the second bonding pad through a bonding wire or a bonding material.

14 . The snubber circuit of claim 1 , wherein the chip package further comprises a die pad, and the transistor die is set on the die pad by an adhesion layer.

15 . The snubber circuit of claim 1 , wherein the first bonding pad, the second bonding pad, and the third bonding pad are electrically connected to the two pins through flip chip bonding.

Assignees

• Fsp Tech Inc

Inventors

• Lin Kuo-Fan

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title