Snubber circuit and buffering method for snubber circuit

Patent metadata

Field	Value
Publication number	US-9455635-B2
Application number	US-201414465855-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Aug 22, 2013
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A snubber circuit includes a capacitor and a buffer device. The buffer device has a first terminal and a second terminal. The first terminal is electrically connected to the capacitor. When the buffer device operates in a first conduction mode, a charge current flows from the second terminal to the first terminal through the buffer device. When the buffer device switches from the first conduction mode to a second conduction mode, the buffer device generates a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal.

First claim

What is claimed is:

1. A snubber circuit, comprising:
a capacitor; and
a buffer device, having a first terminal and a second terminal, wherein the first terminal is electrically connected to the capacitor; when the buffer device operates in a first conduction mode, a charge current flows from the second terminal to the first terminal through the buffer device; and when the buffer device switches from the first conduction mode to a second conduction mode, the buffer device generates a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal, and a voltage signal at the second terminal converges gradually after the buffer device enters the second conduction mode;

wherein the relative maximum voltage level is further lower than the voltage level at the second terminal generated when the discharge current flows from the first terminal to the second terminal and reaches a minimum value.

2. The snubber circuit of claim 1 , wherein when the buffer device operates in the first conduction mode, the charge current flows through the buffer device to charge the capacitor; and when the buffer device operates in the second conduction mode, the discharge current flows through the buffer device to discharge the capacitor.

3. The snubber circuit of claim 1 , wherein when the buffer device switches from the first conduction mode to the second conduction mode, the charge current decreases to zero before the buffer device generates the discharge current.

4. The snubber circuit of claim 1 , wherein the buffer device comprises:
a charge storage device;
a first conversion circuit, coupled to the charge storage device and electrically connected between the first terminal and the second terminal, the first conversion circuit arranged for converting the charge current into charges, and storing the converted charges into the charge storage device when the buffer device operates in the first conduction mode; and
a second conversion circuit, coupled to the charge storage device and electrically connected between the first terminal and the second terminal, the second conversion circuit arranged for converting the charges stored in the charge storage device to generate the discharge current when the buffer device switches from the first conduction mode to the second conduction mode.

5. The snubber circuit of claim 4 , wherein when the buffer device switches from the first conduction mode to the second conduction mode, the first conversion circuit converts the charge current until the charge current decreases to zero, and then the second conversion circuit converts the charges stored in the charge storage device to generate the discharge current.

6. The snubber circuit of claim 1 , further comprising:
a resistive element, coupled in parallel with the capacitor, the resistive element arranged for adjusting a voltage drop across the capacitor.

7. The snubber circuit of claim 1 , wherein the buffer device comprises an NPN bipolar junction transistor, an emitter of the NPN bipolar junction transistor is electrically connected to the second terminal, a collector of the NPN bipolar junction transistor is electrically connected to the first terminal, and a base of the NPN bipolar junction transistor is electrically connected to the emitter.

8. The snubber circuit of claim 1 , wherein the buffer device comprises a PNP bipolar junction transistor, a collector of the PNP bipolar junction transistor is electrically connected to the second terminal, an emitter of the PNP bipolar junction transistor is electrically connected to the first terminal, and a base of the PNP bipolar junction transistor is electrically connected to the emitter.

9. A buffering method for a snubber circuit, comprising:
when a buffer device of the snubber circuit operates in a first conduction mode, conducting a charge current flowing through the buffer device, wherein a first terminal of the buffer device is electrically connected to a capacitor of the snubber circuit, and the charge current flows from a second terminal of the buffer device to the first terminal through the buffer device; and
when the buffer device switches from the first conduction mode to a second conduction mode, generating a discharge current which flows from the first terminal to the second terminal through the buffer device over a specific period of time, such that after the buffer device enters the second conduction mode, a relative maximum voltage level appearing first at the second terminal is lower than a voltage level at the first terminal, and a voltage signal at the second terminal converges gradually after the buffer device enters the second conduction mode;

wherein the relative maximum voltage level is further lower than a voltage level at the second terminal generated when the discharge current flows from the first terminal to the second terminal and reaches a minimum value.

10. The buffering method of claim 9 , wherein the step of generating the discharge current is performed after the charge current decreases to zero.

11. The buffering method of claim 9 , wherein the step of conducting the charge current flowing through the buffer device comprises:
converting the charge current into charges, and storing the converted charges; and
the step of generating the discharge current which flows from the first terminal to the second terminal through the buffer device comprises:
converting the stored charges to generate the discharge current.

12. The buffering method of claim 11 , wherein the step of converting the stored charges to generate the discharge current is performed after the charge current decreases to zero.

13. The buffering method of claim 9 , further comprising:
utilizing a resistive element coupled in parallel with the capacitor to adjust a voltage drop across the capacitor.

14. The buffering method of claim 9 , wherein the buffer device comprises an NPN bipolar junction transistor, and the buffering method further comprises:
electrically connecting an emitter of the NPN bipolar junction transistor to the second terminal;
electrically connecting a collector of the NPN bipolar junction transistor to the first terminal; and
electrically connecting a base of the NPN bipolar junction transistor to the emitter.

15. The buffering method of claim 9 , wherein the buffer device comprises a PNP bipolar junction transistor, and the buffering method further comprises:
electrically connecting a collector of the PNP bipolar junction transistor to the second terminal;
electrically connecting an emitter of the PNP bipolar junction transistor to the first terminal; and
electrically connecting a base of the PNP bipolar junction transistor to the emitter.

Assignees

• Fsp Tech Inc

Inventors

• Lin Kuo-Fan

Classifications

• Y02B70/1491

  Cross-Sectional Technologies · mapped topic

• H02M3/335 Primary

  using semiconductor devices only · CPC title

• H02M3/33507 Primary

  with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title

• H02M2001/342

  Electricity · mapped topic

• H02M2001/344

  Electricity · mapped topic