Semiconductor package for III-nitride transistor stacked with diode

Patent metadata

Field	Value
Publication number	US-9530774-B2
Application number	US-201514620596-A
Country	US
Kind code	B2
Filing date	Feb 12, 2015
Priority date	Mar 2, 2011
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

First claim

The invention claimed is:

1. A two-terminal semiconductor package comprising:
a diode;
a III-nitride transistor;
a first terminal of said package coupled to a drain of said III-nitride transistor;
a second terminal of said package coupled to an anode of said diode;
a cathodc of said diode mechanically and electrically coupled to a source of said III-nitride transistor;
wherein said first terminal and said second terminal are coupled respectively to a first lead and a second lead of said semiconductor package;
a single conductive connector mechanically connected to said second lead, a gate of said III-nitride transistor, and said anode of said diode.

2. The semiconductor package of claim 1 , wherein said gate of said III-nitride transistor is coupled to said anode of said diode, thereby forming a cascoded switch comprising said III-nitride transistor and said diode.

3. The semiconductor package of claim 2 , wherein said a single conductive connector comprises a ribbon.

4. The semiconductor package of claim 2 , wherein said a single conductive connector comprises a clip.

5. The semiconductor package of claim 2 , wherein a said single connector comprises a wirebond.

6. The semiconductor package of claim 1 , wherein said diode is a silicon diode.

7. The semiconductor package of claim 1 , wherein said III-nitride transistor is selected from the group consisting of a GaN FET and a GaN HEMT.

8. The semiconductor package of claim 1 , wherein said III-nitride transistor comprises a depletion-mode GaN.

9. A two-terminal semiconductor package comprising:
a diode;
a III-nitride transistor;
a first terminal of said package coupled to a drain of said III-nitride transistor;
a second terminal of said package coupled to an anode of said diode;
a cathode of said diode mechanically and electrically coupled to a source of said III-nitride transistor;
wherein said first terminal and said second terminal are coupled respectively to a first lead and a second lead of said semiconductor package;
a single conductive connector mechanically connected to said second lead, a gate of said III-nitride transistor, and said anode of said diode;
wherein said a single conductive connector comprises a clip.

10. The semiconductor package of claim 9 , wherein said diode is a silicon diode.

11. The semiconductor package of claim 9 , wherein said III-nitride transistor is selected from the group consisting of a GaN FET and a GaN HEMT.

12. The semiconductor package of claim 9 , wherein said III-nitride transistor comprises a depletion-mode GaN.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Lin Heny
• Zhang Jason
• Guerra Alberto

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title