Waveguide coupler

Patent metadata

Field	Value
Publication number	US-2016276731-A1
Application number	US-201615167768-A
Country	US
Kind code	A1
Filing date	May 27, 2016
Priority date	Oct 22, 2012
Publication date	Sep 22, 2016
Grant date	—

Abstract

An apparatus is provided. In the apparatus, there is an antenna package and an integrated circuit (IC). A circuit trace assembly is secured to the IC. A coupler (with an antenna assembly and a high impedance surface (HIS)) is secured to the circuit trace assembly. An antenna assembly has a window region, a conductive region that substantially surrounds the window region, a circular patch antenna that is in communication with the IC, and an elliptical patch antenna that is located within the window region, that is extends over at least a portion of the circular patch antenna, and that is in communication with the circular patch antenna. The HIS substantially surrounds the antenna assembly.

First claim

1 . A method comprising:
forming a first metallization layer over the substrate such that the first metallization layer includes first and second circular patch antennas that are symmetrically aligned with one another; forming a second metallization layer over the first metallization layer, wherein the second metallization layer has first, second, and third portions, and wherein the first and second portions of the second metallization layer are in communication with the first and second patch antennas, respectively; forming a third metallization layer over the second metallization layer, wherein the third metallization layer has first, second, and third portions, and wherein the first, second, and third portions of the third metallization layer are in communication with the first, second, and third portions of the second metallization layer, respectively; and forming a fourth metallization layer over the third metallization layer, wherein the fourth metallization layer has first, second, and third portions, and wherein the first, second, and third portions of the fourth metallization layer are in communication with the first, second, and third portions of the third metallization layer, respectively, and wherein the first and second portions of the fourth metallization layer are located within a opening in the third portion of the fourth metallization layer that defines a window region, and wherein the first and second portions of the fourth metallization layer formed first and second elliptical patch antennas that are symmetrically aligned with one another.

2 . The method of claim 1 , wherein the method further comprises:
forming first and second pad on a first side of the substrate; and forming first and second vias that extend from the first side to a second side, wherein the first and second vias are substantially and respectively aligned with the first and second pads, and wherein the first metallization layer is formed over the second side of the substrate.

3 . The method of claim 2 , wherein the method further comprises:
forming a first dielectric layer between the first and second metallization layers; and forming third and fourth vias that extend between the first and second metallization layers, wherein the third and fourth vias are in communication with the first and second circular patch antennas, respectively, and wherein the first and second portions of the second metallization layer are in communication with the third and fourth vias, respectively.

4 . The method of claim 3 , wherein the method further comprises:
forming a second dielectric layer between the second and third metallization layers; forming fifth and sixth vias that extend between the second and third metallization layers, wherein the fifth and sixth vias are in communication with the first and second portions of the second and third metallization layers, respectively; and forming a set of seventh vias that extend between the second and third metallization layers, wherein the set of seventh vias are in communication with the third portions of the second and third metallization layers.

5 . The method of claim 4 , wherein the method further comprises:
forming a third dielectric layer between the third and fourth metallization layers; forming eighth and ninth vias that extend between the third and fourth metallization layers, wherein the eighth and ninth vias are in communication with the first and second portions of the third and fourth metallization layers, respectively; and forming a set of tenth vias that extend between the third and fourth metallization layers, wherein the set of tenth vias are in communication with the third portions of the third and fourth metallization layers.

6 . The method of claim 5 , wherein the method further comprises:
securing a circuit trace assembly to the substrate; and securing an IC to the circuit trace assembly.

Assignees

• Texas Instruments Inc

Inventors

• Seok Eunyoung
• Ramaswamy Srinath
• Ginsburg Brian B
• Rentala Vijay B
• Haroun Baher

Classifications

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K3/4038

  Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence) · CPC title

• H01P5/08

  for linking dissimilar lines or devices (H01P1/16, H01P5/04 take precedence; linking lines of the same kind but with different dimensions H01P5/02) · CPC title

• H05K3/20

  by affixing prefabricated conductor pattern {(H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence)} · CPC title

• H01Q9/0407

  Substantially flat resonant element parallel to ground plane, e.g. patch antenna (dipole H01Q9/285; monopole H01Q9/40) · CPC title