Row hammer monitoring based on stored row hammer threshold value

Patent metadata

Field	Value
Publication number	US-2016276015-A1
Application number	US-201615170606-A
Country	US
Kind code	A1
Filing date	Jun 1, 2016
Priority date	Nov 30, 2012
Publication date	Sep 22, 2016
Grant date	—

Abstract

Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

First claim

1 - 15 . (canceled)

16 . An apparatus comprising:
a detection logic to obtain a value, the value to indicate a maximum number of accesses to a target row of a memory within a time period; and a memory controller to cause the memory to perform a refresh of at least one row physically adjacent to the target row based at least in part on a comparison between the value and a number of accesses to the target row within the time period.

17 . The apparatus of claim 16 , wherein the at least one row physically adjacent to the target row comprises at least one victim row.

18 . The apparatus of claim 16 , further comprising the memory communicatively coupled with the detection logic and the memory controller, the memory comprising multiple physical rows of memory cells.

19 . The apparatus of claim 16 , wherein the memory controller comprises the detection logic.

20 . The apparatus of claim 18 , wherein the memory device comprises the detection logic.

21 . The apparatus of claim 18 , further comprising
a network interface to store information to the memory; and a display device configured to provide a user display based on data accessed from the memory.

22 . The apparatus of claim 16 , further comprising a register to store configuration information for the memory, the register to store the value.

23 . The apparatus of claim 16 , wherein the number of accesses to the target row within the time period is based on identification by the detection logic of an address associated with an activate command and maintenance of a count of a number of accesses to the address.

24 . The apparatus of claim 16 , wherein the comparison between the value and a number of accesses to the target row within the time period comprises a determination of whether the number of accesses to the target row within the time period reaches the value.

25 . The apparatus of claim 16 , wherein the comparison between the value and a number of accesses to the target row within the time period comprises a determination of whether the number of accesses to the target row within the time period exceeds the value.

26 . The apparatus of claim 16 , wherein the detection logic comprises one or more of the circuitry comprises any or a combination of: software executed by one or more processors, hardware, or firmware and the memory controller comprises any or a combination of: software executed by one or more processors, hardware, or firmware.

27 . A memory comprising:
logic to cause a refresh of at least one row physically adjacent to a target row in response to receipt of a command to refresh, the command to refresh based at least on a condition in which a number of accesses to the target row within a time period reaches or exceeds a value.

28 . The memory of claim 27 , wherein the at least one row physically adjacent to the target row comprises at least one victim row.

29 . The memory of claim 27 , wherein the memory comprises multiple physical rows of memory cells including the target row.

30 . The memory of claim 27 , further comprising a register to store configuration information for the memory, the register to store the value and the value to indicate a maximum number of accesses to the target row of a memory within the time period.

31 . The memory of claim 27 , wherein the condition in which a number of accesses to the target row within a time period reaches or exceeds a value is based on a count of a number of received activate commands during the time period.

32 . The memory of claim 27 , wherein the logic comprises one or more of the circuitry comprises any or a combination of: software executed by one or more processors, hardware, or firmware.

33 . At least one computer-readable storage medium, that when executed by one or more processors, cause the one or more processors to:
obtain a value, the value to indicate a maximum number of accesses to a target row of a memory within a time period; and cause the memory to perform a refresh of at least one row physically adjacent to the target row based at least in part on a comparison between the value and a number of accesses to the target row within the time period.

34 . The at least one computer-readable medium of claim 33 , wherein the at least one row physically adjacent to the target row comprises at least one victim row.

35 . The at least one computer-readable medium of claim 33 , wherein the comparison between the value and a number of accesses to the target row within the time period comprises a determination of whether the number of accesses to the target row within the time period reaches the value.

36 . The at least one computer-readable medium of claim 33 , wherein the comparison between the value and a number of accesses to the target row within the time period comprises a determination of whether the number of accesses to the target row within the time period exceeds the value.

37 . The at least one computer-readable medium of claim 33 , wherein the number of accesses to the target row within the time period is based on identification of an address associated with an activate command and a count of a number of accesses to the address.

38 . A method comprising:
obtaining a value, the value to indicate a maximum number of accesses to a target row of a memory within a time period; and causing the memory to perform a refresh of at least one row physically adjacent to the target row based at least in part on a comparison between the value and a number of accesses to the target row within the time period.

39 . The method of claim 38 , wherein the at least one row physically adjacent to the target row comprises at least one victim row.

40 . The method of claim 38 , wherein the number of accesses to the target row within the time period is based on identifying an address associated with an activate command and a maintaining a count of a number of accesses to the address.

41 . The method of claim 38 , wherein the comparison between the value and a number of accesses to the target row within the time period comprises a determination of whether the number of accesses to the target row within the time period reaches the value.

42 . The method of claim 38 , wherein the comparison between the value and a number of accesses to the target row within the time period comprises a determination of whether the number of accesses to the target row within the time period exceeds the value.

Assignees

• Intel Corp

Inventors

• Bains Kuljit S
• Halbert John B

Classifications

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C29/50012

  of timing · CPC title

• G11C2029/0409

  Online test · CPC title