Implementing eFuse visual security of stored data using EDRAM

Patent metadata

Field	Value
Publication number	US-9514841-B1
Application number	US-201514948701-A
Country	US
Kind code	B1
Filing date	Nov 23, 2015
Priority date	Nov 23, 2015
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuity having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

First claim

What is claimed is:

1. A circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), said circuit comprising:
an EDRAM;
an eFuse having an initial state of logical 0, said EDRAM and said eFuse having a same bit count; and
an exclusive OR (XOR) gate receiving respective outputs of said eFuse and said EDRAM, said XOR gate providing an output data combination enabling EDRAM random data to be known at wafer test and enabling said eFuse to be programmed to provide any logical value from the output data combination.

2. The circuit as recited in claim 1 wherein each address input for said EDRAM and said eFuse use a same pin connected to a same physical wire, avoiding reads from getting out of synchronization.

3. The circuit as recited in claim 2 wherein said eFuse has a busy signal used to indicate that the read has not completed, said eFuse busy signal used to provide a control signal for reading said XOR gate.

4. The circuit as recited in claim 1 wherein a read complete signal for reading said XOR gate is generated by identifying a required time interval to prevent the EDRAM data from being read without proper filtering by the eFuse.

5. The circuit as recited in claim 2 includes enabling data read of said EDRAM during the wafer test, responsive to read address and read order being linked between said EDRAM and said eFuse.

6. The circuit as recited in claim 1 includes a capture latch receiving respective outputs of said XOR gate.

7. A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:
a circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), said circuit comprising:
an EDRAM;
an eFuse having an initial state of logical 0, said EDRAM and said eFuse having a same bit count; and
an exclusive OR (XOR) gate receiving respective outputs of said eFuse and said EDRAM, said XOR gate providing an output data combination enabling EDRAM random data to be known at wafer test and enabling said eFuse to be programmed to provide any logical value from the output data combination, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.

8. The design structure of claim 7 , wherein the design structure comprises a netlist, which describes said circuit.

9. The design structure of claim 7 , wherein the design structure resides on storage medium as a data format used for exchanging layout data of integrated circuits.

10. The design structure of claim 7 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

11. The design structure of claim 7 , includes each address input for said EDRAM and said eFuse use a same pin connected to a same physical wires, avoiding reads from getting out of synchronization.

12. The design structure of claim 11 , wherein said eFuse has a busy signal used to indicate that the read has not completed, said eFuse busy signal used to provide a control signal for reading said XOR gate.

13. The design structure of claim 7 , includes a capture latch receiving respective outputs of said XOR gate.

14. The design structure of claim 7 , includes enabling data read of said EDRAM during the wafer test, responsive to read address and read order being linked between said EDRAM and said eFuse.

15. The design structure of claim 14 , said eFuse starting with said initial state of logical 0 for reading the EDRAM data during the wafer test.

Assignees

• IBM

Inventors

• Christensen Todd A
• Erickson Karl R
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4078 Primary

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title