Split-gate flash memory with improved program efficiency

Patent metadata

Field	Value
Publication number	US-2016268387-A1
Application number	US-201514643558-A
Country	US
Kind code	A1
Filing date	Mar 10, 2015
Priority date	Jun 23, 2011
Publication date	Sep 15, 2016
Grant date	—

Abstract

A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.

First claim

1 . A device comprising:
a memory gate stack over a channel region; and a word gate having an uppermost surface in an upper portion and a lower surface in a lower portion, the word gate extending from the uppermost surface at an upper surface of the memory gate stack to the lower surface of the word gate below an upper surface of a substrate at source and drain regions, wherein the upper portion of the word gate and the lower portion of the word gate have the same width, and wherein the upper surface of the memory gate stack and the uppermost surface of the word gate are substantially coplanar.

2 . The device according to claim 1 , further comprising a band engineered channel as the channel region.

3 . The device according to claim 2 , wherein the band engineered channel comprises one or more layers.

4 . The device according to claim 1 , wherein the channel region comprises a buried channel in the substrate.

5 . The device according to claim 2 , comprising an opening through the channel region, wherein the word gate is formed in the opening.

6 . The device according to claim 1 , wherein the word gate extends below the channel region.

7 . The device according to claim 1 , including a split gate non-volatile memory device, the split-gate non-volatile memory device comprising the memory gate stack and the word gate.

8 . A device comprising:
a memory gate stack over a channel region; an opening formed in the memory gate stack; a word gate, having an uppermost surface in an upper portion and a lower surface in a lower portion, the word gate having sidewall spacers on side surfaces thereof and the word gate extending from the upper surface at an upper surface of the memory gate stack to the lower surface of the word gate below an upper surface of a substrate at the channel region and below an upper surface of the substrate at source and drain regions, in the opening, wherein the lower portion of the word gate contacts both the channel region and a source or drain region, and wherein the upper portion of the word gate and the lower portion of the word gate have the same width; and wherein the upper surface of the memory gate stack and the uppermost surface of the word gate are substantially coplanar.

9 . The device according to claim 8 , further comprising:
a band engineered channel as the channel region.

10 . The device according to claim 9 , wherein the opening extends through the band engineered channel.

11 . The device according to claim 10 , wherein the word gate extends through the band engineered channel.

12 . The device according to claim 8 , further comprising a buried channel as the channel region.

13 . The device according to claim 12 , wherein the opening extends below the buried channel.

14 . A device comprising:
a memory gate stack over a channel region, the memory gate stack comprising an upper surface; and a word gate extending below an upper surface of a substrate having the channel region, the word gate comprising an uppermost surface, wherein the uppermost surface of the word gate is substantially coplanar with the upper surface of the memory gate stack.

15 . The device according to claim 14 , wherein the channel region comprises a band engineered channel.

16 . The device according to claim 15 , wherein the band engineered channel comprises one or more layers.

17 . The device according to claim 14 , wherein the channel region comprises a buried channel in the substrate.

18 . The device according to claim 15 , comprising an opening through the channel region, wherein the word gate is formed in the opening.

19 . The device according to claim 14 , wherein the word gate extends below the channel region.

20 . The device according to claim 14 including a split gate non-volatile memory device, the split-gate non-volatile memory device comprising the memory gate stack and the word gate.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Toh Eng Huat
• Tan Shyue Seng (Jason)

Classifications

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D30/6894

  having one gate at least partly in a trench · CPC title

• H10D30/699

  having the gate at least partly formed in a trench · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title