Fabrication method of vertical type semiconductor memory apparatus
US-9196832-B2 · Nov 24, 2015 · US
Semiconductor memory device
US2016268342A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016268342-A1 |
| Application number | US-201514838535-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 28, 2015 |
| Priority date | Mar 12, 2015 |
| Publication date | Sep 15, 2016 |
| Grant date | — |
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Abstract
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According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor memory device comprising: a plurality of first resistance-change memory elements of a two-terminal type; a second resistance-change memory element of a two-terminal type; a rectifier element of a two-terminal type; a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element; and a global bit line connected to the other end of the second resistance-change memory element. 2 . The device of claim 1 , wherein the second resistance-change memory element is set to a high-resistance state by supplying a high-resistance-state setting signal between the other end of the rectifier element and the global bit line, and the second resistance-change memory element is set to a low-resistance state having a resistance lower than that in the high-resistance state by supplying a low-resistance-state setting signal between the other end of the rectifier element and the global bit line, and data is written and read for a desired one of the first resistance-change memory elements connected to the second resistance-change memory element set to the low-resistance state. 3 . The device of claim 2 , wherein the first resistance-change memory elements, the second resistance-change memory element and the rectifier element are stacked vertically. 4 . The device of claim 3 , wherein the first resistance-change memory elements and the second resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu. 5 . The device of claim 2 , wherein the first resistance-change memory elements and the second resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu. 6 . The device of claim 1 , wherein the first resistance-change memory elements, the second resistance-change memory element and the rectifier element are stacked vertically. 7 . The device of claim 6 , wherein the first resistance-change memory elements and the second resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu. 8 . The device of claim 1 , wherein the first resistance-change memory elements and the second resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu. 9 . A semiconductor memory device comprising: a plurality of first resistance-change memory elements of a two-terminal type; a second resistance-change memory element of a two-terminal type; a third resistance-change memory element of a two-terminal type; a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the third resistance-change memory element; and a global bit line connected to the other end of the second resistance-change memory element. 10 . The device of claim 9 , wherein the second resistance-change memory element is set to a high-resistance state by supplying a high-resistance-state setting signal between the other end of the third resistance-change memory element and the global bit line, and the second resistance-change memory element is set to a low-resistance state having a resistance lower than that in the high-resistance state by supplying a low-resistance-state setting signal between the other end of the third resistance-change memory element and the global bit line, and data is written and read for a desired one of the first resistance-change memory elements connected to the second resistance-change memory element set to the low-resistance state. 11 . The device of claim 10 , wherein the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are stacked vertically. 12 . The device of claim 11 , wherein the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu. 13 . The device of claim 10 , wherein the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu. 14 . The device of claim 9 , wherein the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are stacked vertically. 15 . The device of claim 14 , wherein the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu. 16 . The device of claim 9 , wherein the first resistance-change memory elements, the second resistance-change memory element and the third resistance-change memory element are selected from a chalcogenide material including GeSbTe, a superlattice material of GeTe and SbTe, a binary or ternary transition metal oxide material, an oxide material containing Au or Cu, and a chalcogenide material containing Au or Cu.
Assignees
Inventors
Classifications
- H01L27/2463Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Phase change RAM [PCRAM, PRAM] devices · CPC title
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Frequently asked questions
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- What does patent US2016268342A1 cover?
- According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H01L27/2463. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Sep 15 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).