Structures to avoid floating resurf layer in high voltage lateral devices

Patent metadata

Field	Value
Publication number	US-2016254346-A1
Application number	US-201514634801-A
Country	US
Kind code	A1
Filing date	Feb 28, 2015
Priority date	Feb 28, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate comprising p-type semiconductor material; a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;
a RESURF layer of p-type semiconductor material disposed in the substrate over at least a portion of the drain drift region, the RESURF layer extending from the drain drift region to a top surface of the substrate; and a lateral shunt of p-type semiconductor material disposed in the substrate, the lateral shunt extending to the top surface of the substrate and extending laterally from the RESURF layer to the body.

2 . The semiconductor device of claim 1 , wherein the RESURF layer is 1 micron to 5 microns thick, and has an average doping density of 1×10 16 cm −3 to 1×10 17 cm −3 .

3 . The semiconductor device of claim 1 , wherein the lateral shunt is 1 micron to 5 microns thick, and has an average doping density of 2×10 16 cm −3 to 2×10 17 cm −3 .

4 . The semiconductor device of claim 1 , wherein the lateral shunt is 1 micron to 5 microns wide.

5 . The semiconductor device of claim 1 , wherein a resistance of the lateral shunt is 1000 ohms to 10000 ohms.

6 . The semiconductor device of claim 1 , comprising a plurality of instances of the lateral shunt.

7 . The semiconductor device of claim 1 , wherein the LDNMOS transistor comprises a threshold adjustment region of p-type semiconductor disposed in the body.

8 . The semiconductor device of claim 1 , wherein the RESURF layer is laterally recessed adjacent to the lateral shunt by 1 micron to 2 microns.

9 . A semiconductor device, comprising:
a substrate comprising p-type semiconductor material; an LDNMOS transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;
a RESURF layer of p-type semiconductor material disposed in the substrate over at least a portion of the drain drift region, the RESURF layer extending from the drain drift region to a top surface of the substrate; and a vertical shunt of p-type semiconductor material disposed in the substrate, the lateral shunt extending vertically through an opening in the drain drift region, from the RESURF layer to the p-type semiconductor material below the drain drift region.

10 . The semiconductor device of claim 9 , wherein the RESURF layer is 1 micron to 5 microns thick, and has an average doping density of 1×10 16 cm −3 to 1×10 17 cm −3 .

11 . The semiconductor device of claim 9 , wherein a width of the vertical shunt is 3 microns to 8 microns.

12 . The semiconductor device of claim 9 , wherein a length of the vertical shunt is 3 microns to 10 microns.

13 . The semiconductor device of claim 9 , wherein the vertical shunt is laterally separated from the body by less than 3 microns.

14 . The semiconductor device of claim 9 , comprising a plurality of instances of the vertical shunt.

15 . The semiconductor device of claim 9 , wherein a resistance of the vertical shunt is 5000 to 50000 ohms.

16 . A semiconductor device, comprising:
a substrate comprising p-type semiconductor material; an LDNMOS transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;
a RESURF layer of p-type semiconductor material disposed in the substrate over at least a portion of the drain drift region, the RESURF layer extending from the drain drift region to a top surface of the substrate; and an interconnect shunt comprising a p-type shunt contact region in the substrate in an active area over the RESURF layer, a contact over the p-type shunt contact region, and a metal interconnect on the contact, the interconnect shunt extending from the RESURF layer to a source node of the LDNMOS transistor.

17 . The semiconductor device of claim 16 , wherein the RESURF layer is 1 micron to 5 microns thick, and has an average doping density of 1×10 16 cm −3 to 1×10 17 cm −3 .

18 . The semiconductor device of claim 16 , wherein the interconnect shunt comprises metal silicide disposed on the shunt contact region under the contact.

19 . The semiconductor device of claim 16 , comprising a plurality of instances of the interconnect shunt.

20 . The semiconductor device of claim 16 , wherein the metal interconnect of the interconnect shunt comprises aluminum.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Hower Philip L
• Lin John
• Mathur Guru
• Balster Scott G
• Bulucea Constantin
• Lee Zachary K
• Pendharkar Sameer P

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title