Low temperature fabrication of lateral thin film varistor

Patent metadata

Field	Value
Publication number	US-9536732-B2
Application number	US-201514885512-A
Country	US
Kind code	B2
Filing date	Oct 16, 2015
Priority date	Feb 26, 2015
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

First claim

What is claimed is:

1. A method of forming a lateral thin film varistor comprising:
forming a continuous layer comprising alternating regions of a first metal oxide layer and a second metal oxide layer between two laterally spaced electrodes using a sputtering process followed by an annealing process.

2. The method of claim 1 , wherein the first metal oxide layer comprises zinc oxide.

3. The method of claim 1 , further comprising:
doping the first metal oxide layer with aluminum oxide.

4. The method of claim 1 , wherein the second metal oxide layer comprises bismuth oxide.

5. The method of claim 1 , further comprising:
doping the second metal oxide layer with aluminum oxide.

6. The method of claim 1 , wherein the annealing process is carried out in an inert gas atmosphere.

7. The method of claim 1 , wherein the annealing process comprises:
heating the continuous layer to a temperature not exceeding a maximum temperature reached during the sputtering process.

8. A method of forming a lateral thin film varistor comprising:
forming a first metal oxide layer on a dielectric layer;
removing a portion of the first metal oxide layer to form a first opening, the first opening exposing an upper surface of the dielectric layer;
forming an isolation layer on the dielectric layer, the isolation layer adjacent to the first metal oxide layer and in the first opening;
removing a portion of the isolation layer from the first opening to expose the upper surface of the dielectric layer;
forming a second metal oxide layer in the opening, wherein the first metal oxide layer and the second metal oxide layer comprise a continuous alternating layer;
removing a portion of the isolation layer adjacent to the continuous alternating layer to form a second opening, the second opening exposing an upper surface of the dielectric layer; and
forming an electrode in the second opening, the electrode adjacent to and contacting the continuous alternating layer.

9. The method of claim 8 , wherein the forming of the first metal oxide layer on the dielectric layer comprises:
depositing zinc oxide using a sputtering process.

10. The method of claim 8 , wherein the forming of the second metal oxide layer in the opening comprises:
depositing bismuth oxide using a sputtering process.

11. The method of claim 8 , further comprising:
doping the first metal oxide layer with aluminum oxide.

12. The method of claim 8 , further comprising:
doping the second metal oxide layer with aluminum oxide.

13. The method of claim 8 , further comprising:
performing an annealing process.

14. The method of claim 13 , wherein the annealing process comprises:
heating the first metal oxide layer and the second metal oxide layer to a temperature not exceeding approximately 350 ° C.

15. The method of claim 13 , wherein the annealing process comprises:
heating the second metal oxide layer to a temperature not exceeding approximately 350 ° C.

16. The method of claim 13 , wherein the annealing process comprises:
heating the first metal oxide layer and the second metal oxide layer to a temperature not exceeding a maximum temperature reached during the sputtering process.

17. The method of claim 8 , further comprising:
forming a wiring level on the continuous alternating layer, the electrode, and the isolation layer;
forming conductive features in the wiring level, the conductive features in electrical contact with the electrode.

18. The method according to claim 1 , wherein the forming a continuous layer comprising alternating regions of a first metal oxide layer and a second metal oxide layer comprises forming said continuous layer on a dielectric layer.

19. The method according to claim 1 , wherein the annealing process includes heating the first metal oxide layer and the second metal oxide layer to a temperature not exceeding approximately 350 ° C.

20. The method according to claim 19 , wherein the annealing process further comprises:
heating the second metal oxide layer to a temperature not exceeding approximately 350 ° C.; and
heating the first metal oxide layer and the second metal oxide layer to a temperature not exceeding a maximum temperature reached during the sputtering process.

Assignees

• IBM

Inventors

• Gambino Jeffrey P
• Graf Richard S
• Mandal Sudeep

Classifications

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title