Selectable peripheral logic in programmable apparatus

Patent metadata

Field	Value
Publication number	US-10540310-B2
Application number	US-201916378984-A
Country	US
Kind code	B2
Filing date	Apr 9, 2019
Priority date	May 15, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A programmable apparatus for executing a function is disclosed. The programmable apparatus includes a physical interface configured to be connected with an external apparatus. The programmable apparatus also includes a function logic circuit configured to execute the function on the programmable apparatus. The programmable apparatus further includes a plurality of peripheral logic circuits, each of which is configured to connect the function logic circuit with the physical interface using a respective protocol. The programmable apparatus also includes a selector circuit configured to select one from among the plurality of the peripheral logic circuits to activate.

First claim

What is claimed is:

1. A computer system for developing a function on a programmable apparatus, the programmable apparatus including a physical interface, the system comprising:
a non-transitory computer readable storage medium having program instructions embodied therewith; and
a processor communicatively coupled to the non-transitory computer readable storage medium, wherein the processor is configured to execute the program instructions to cause the processor perform a method comprising:
reading a data structure including a peripheral logic design for a plurality of peripheral logic circuits and a selector design for a selector circuit on the programmable apparatus, wherein:
the plurality of the peripheral logic circuits are configured to share a hardware intellectual property block connected to the physical interface in the programmable apparatus,
the hardware intellectual property block includes a register holding a value of the predetermined setting parameter, and the value of the predetermined setting parameter is configurable via the physical interface and by a non-volatile memory in starting or restarting the programmable apparatus;

reading a code of high level language, the code describing the function; and
passing the code and the data structure to a compiler to generate configuration data representing designs and internal states of elements in the programmable apparatus, the programmable apparatus being configured by the configuration data to have the plurality of the peripheral logic circuits, the selector circuit and a function logic circuit for executing the function, each peripheral logic circuit being configured to connect the function logic circuit with the physical interface using a respective protocol, the selector circuit being configured to select one peripheral logic circuit from among the plurality of the peripheral logic circuits to activate,
wherein the selector design comprises:
a first selector design for a first selector, the first selector being configured to connect the physical interface with one of the plurality of peripheral logic circuits,
a second selector design for a second selector, the second selector being configured to connect the function logic circuit with one of the plurality peripheral logic circuits, and
a selector controller design for a selector controller, the selector controller being configured to control states of the first and second selectors based on a predetermined setting parameter, and

wherein the compiler is OpenCL kernel compiler, the programmable apparatus is a circuit board including a Field Programmable Gate Array (FPGA), and the function logic circuit implements a kernel corresponding to a host application on a host computer, the function logic circuit, the plurality of the peripheral logic circuits and the selector circuit being implemented at least in part by using logic blocks of the FPGA.

Assignees

• IBM

Inventors

• Kawai Yutaka
• Miwa Yohichi

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F9/223

  Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems · CPC title

• G06F15/7892

  Reconfigurable logic embedded in CPU, e.g. reconfigurable unit · CPC title

• G06F13/387 Primary

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title