Laser annealing systems and methods with ultra-short dwell times

US2016240407A9 · US · A9

Patent metadata
FieldValue
Publication numberUS-2016240407-A9
Application numberUS-201414490446-A
CountryUS
Kind codeA9
Filing dateSep 18, 2014
Priority dateJun 11, 2012
Publication dateAug 18, 2016
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 μs to about 100 μs. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed.

First claim

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What is claimed is: 1 . An ultra-fast laser annealing system for annealing a semiconductor wafer having a wafer surface, comprising: a primary laser system that forms a primary image on the wafer surface at a first wavelength, wherein the primary image increases an amount of absorption of light at a second wavelength; a secondary laser system that forms a secondary image on the wafer surface at the second wavelength, wherein the secondary image resides at least partially within the primary image; and wherein the secondary laser system includes a scanning optical system that scans the secondary image over the wafer surface to define a scan path, wherein the secondary image has a dwell time of between 1 μs and 100 μs, thereby causing the wafer surface to reach a peak annealing temperature T AP between 350° C. and 1250° C. 2 . The ultra-fast laser annealing system of claim 1 , further comprising: a thermal emission detector system operably arranged to detect thermal emission radiation from the wafer surface at the location of the secondary image and generate a first electrical signal; a collection optical system operably arranged to collect reflected light from the secondary laser beam that reflects from the wafer surface at the location of the secondary image and generate a second electrical signal; a power sensor arranged to measure an amount of power in the secondary laser beam and generate a third electrical signal thereof; a controller operably connected to the thermal emission detector system, the collection optical system, the power sensor and the secondary laser system, the controller configured to receive and process the first, second and third electrical signals and determine therefrom wafer surface temperature T S at the location of the secondary image. 3 . The ultra-fast laser annealing system of claim 2 , wherein the thermal emission detector system and the scanning optical system include overlapping optical path sections. 4 . The ultra-fast laser annealing system of claim 2 , wherein the controller is configured to control an amount of power in the secondary laser beam based on the determined wafer surface temperature T S . 5 . The ultra-fast laser annealing system of claim 4 , wherein the primary and secondary images generate a peak annealing temperature that does not vary over the semiconductor wafer by more than +/−3° C. 6 . The ultra-fast laser annealing system of claim 2 , wherein the scanning optical system includes a scanning mirror operably connected to a mirror driver, wherein the mirror driver is operably connected to and controlled by the controller. 7 . The ultra-fast laser annealing system of claim 1 , wherein the first wavelength is in the range from 300 nm to 650 nm. 8 . The ultra-fast laser annealing system of claim 1 , wherein the second wavelength is in the range from 500 nm to 10.6 microns. 9 . The ultra-fast laser annealing system of claim 1 , wherein the secondary laser system includes a fiber laser having an output power of between 50 watts and 5000 watts. 10 . The ultra-fast laser annealing system of claim 1 , wherein the semiconductor wafer includes a device wafer having thickness in a range: a) from 10 μm to 100 μm, or b) from 500 μm to 1,000 μm. 11 . The ultra-fast laser annealing system of claim 1 , wherein the primary image remains stationary. 12 . The ultra-fast laser annealing system of claim 1 , wherein the secondary image falls entirely within the primary image. 13 . The ultra-fast laser annealing system of claim 1 , wherein the wafer has opposite edges and wherein the primary image extends between the opposite wafer edges. 14 . The ultra-fast laser annealing system of claim 1 , wherein the secondary image defines a line image. 15 . The ultra-fast laser annealing system of claim 1 , wherein the secondary image has a width in the range from 25 μm to 100 μm and a length in the range from 500 μm to 2000 μm. 16 . The ultra-fast laser annealing system of claim 1 , wherein the semiconductor wafer has a device surface and an opposite unpatterned surface, wherein the device surface supports device features having a melt temperature and the unpatterned surface defines the wafer surface, the method further comprising: maintaining the device surface of the product wafer at a temperature below the melt temperature of the device features. 17 . An ultra-fast laser annealing system for annealing a product wafer that includes a device wafer having a device side that supports device features having a melt temperature and an opposite unpatterned side that defines an annealing surface, the system comprising: a laser that generates a laser beam having an annealing wavelength in the range from about 300 nm to about 650 nm; a scanning optical system that receives the laser beam and scans the laser beam over the annealing surface as a scanned image having a dwell time of between 1 μs and 100 μs, thereby causing the annealing surface to reach a peak annealing temperature T AP between 350° C. and 1250° C. while maintaining the device side of the product wafer a temperature below the melt temperature of the device features. 18 . The ultra-fast laser annealing system of claim 17 , wherein the device wafer has a thickness in the range from about 10 μm to about 100 μm. 19 . The ultra-fast laser annealing system of claim 17 , wherein the scanning optical system is configured as an F-theta scanning system. 20 . The ultra-fast laser annealing system of claim 17 , wherein the device features comprise at least one of: CMOS features, aluminum interconnects and copper interconnects. 21 . The ultra-fast laser annealing system of claim 17 , wherein the device surface and the unpatterned surface define a thickness between 500 μm and 1000 μm. 22 . The ultra-fast laser annealing system of claim 17 , wherein the unpatterned surface includes an ion-implant layer, and wherein the scanning of the secondary image causes the ion-implant layer to become conducting.

Assignees

Inventors

Classifications

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • Temperature monitoring · CPC title

  • with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

  • using laser beams · CPC title

  • mainly by radiation · CPC title

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What does patent US2016240407A9 cover?
Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the r…
Who is the assignee on this patent?
Ultratech Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/0436. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 18 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A9). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).