Thin film transistor array panel and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016204266-A1
Application number	US-201514879283-A
Country	US
Kind code	A1
Filing date	Oct 9, 2015
Priority date	Jan 8, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

A thin film transistor array panel and method of manufacturing. The thin film transistor array panel includes a substrate, a first gate electrode positioned on the substrate, a gate insulating layer positioned on the first gate, an oxide semiconductor positioned on the gate insulating layer and including a channel region, at least one etch stopper positioned on the oxide semiconductor, a second gate electrode, a source electrode and a drain electrode positioned on the at least one etch stopper, a passivation layer formed on the second gate electrode, the source electrode and the drain electrode; and a pixel electrode positioned on the passivation layer and connected to the drain electrode, in which the oxide semiconductor includes an N+ region formed in a portion exposed through the at least one etch stopper.

First claim

What is claimed is:

1 . A thin film transistor array panel, comprising:
a substrate; a first gate electrode positioned on the substrate; a gate insulating layer positioned on the first gate; an oxide semiconductor positioned on the gate insulating layer and including at least one channel region; one or more etch stoppers positioned on the oxide semiconductor; a second gate electrode, a source electrode and a drain electrode positioned on at least one of the etch stoppers; a passivation layer formed on the second gate electrode, the source electrode and the drain electrode; and a pixel electrode positioned on the passivation layer and connected to the drain electrode, wherein the oxide semiconductor comprises an N+ region formed in a portion exposed through the at least one etch stopper.

2 . The thin film transistor array panel of claim 1 , wherein:
the N+ region has one side that is in contact with the gate insulating layer, and the N+ region has the other side that is in contact with the source electrode or the drain electrode.

3 . The thin film transistor array panel of claim 2 , wherein:
the N+ region is positioned between the etch stoppers and includes first and second N+ regions positioned at both sides of the first gate electrode.

4 . The thin film transistor array panel of claim 1 , wherein:
the at least one etch stopper includes first to third etch stoppers.

5 . The thin film transistor array panel of claim 4 , wherein:
the first etch stopper is positioned on the first gate electrode, and the second and third etch stoppers are formed at both sides of the first etch stopper and are partially in contact with the oxide semiconductor.

6 . The thin film transistor array panel of claim 5 , wherein:
the second and third etch stoppers are in contact with both ends of the oxide semiconductor and the gate insulating layer.

7 . The thin film transistor array panel of claim 4 , wherein:
the source electrode and the drain electrode cover the second etch stopper and the third etch stopper, respectively.

8 . The thin film transistor array panel of claim 1 , wherein:
the second gate electrode has a narrower width than the first gate electrode.

9 . The thin film transistor array panel of claim 1 , wherein:
the oxide semiconductor includes a titanium-indium-zinc oxide (TIZO) containing a combination of titanium (Ti), indium (In) and zinc (Zn).

10 . The thin film transistor array panel of claim 1 , wherein:
at least one channel region of the oxide semiconductor includes a first channel region and a second channel region, and the first channel region is positioned above the gate insulating layer, and the second channel region is positioned under the first etch stopper.

11 . The thin film transistor array panel of claim 1 , wherein:
the passivation layer includes fluorine-containing silicon oxide (SiOF).

12 . A method of manufacturing a thin film transistor array panel, the method comprising:
forming a first gate electrode on a substrate; forming a gate insulating layer on the first gate electrode; forming an oxide semiconductor including a channel region on the gate insulating layer; forming one or more etch stoppers on the oxide semiconductor; forming an N+ region in an exposed portion of the oxide semiconductor; forming a second gate electrode, a source electrode, and a drain electrode on the at least one etch stopper; and forming a passivation layer on the second gate electrode, the source electrode, and the drain electrode.

13 . The method of claim 12 , wherein:
the forming of the N+ region comprises forming a photo resist (PR) on at least one of the etch stoppers and forming an N+ region using the PR as a mask, wherein the N+ region is formed in a portion exposed through the at least one etch stopper in the oxide semiconductor.

14 . The method of claim 12 , wherein
the forming of the N+ region is performed by one of an ion implantation method and an inductively coupled plasma (ICP) method.

15 . The method of claim 14 , wherein
the inductively coupled plasma method comprises injecting fluorine to form the N+ region.

16 . The method of claim 12 , wherein:
the N+ region has one side that is in contact with the gate insulating layer, and the N+ region has the other side that is in contact with the source electrode or the drain electrode.

17 . The method of claim 16 , wherein:
the N+ region is positioned between the etch stoppers and includes first and second N+ regions positioned at both sides of the first gate electrode.

18 . The method of claim 12 , wherein
the forming of the source electrode and the drain electrode comprises forming the source electrode and the drain electrode to be partially in contact with the oxide semiconductor.

19 . The method of claim 12 , wherein
the forming of the etch stoppers further comprises: forming a first etch stopper on the oxide semiconductor; and forming second and third etch stoppers at both sides of the first etch stopper.

20 . The method of claim 19 , wherein
the forming of the second and third etch stoppers comprises forming the second and third etch stoppers to be in contact with both ends of the oxide semiconductor and the gate insulating layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Seo Ki Seong
• Jo Jung Yun

Classifications

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title

• G02F1/1343

  Electrodes {(reflective electrodes G02F1/133553)} · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title