Array substrate for display device

Patent metadata

Field	Value
Publication number	US-2015144905-A1
Application number	US-201414475182-A
Country	US
Kind code	A1
Filing date	Sep 2, 2014
Priority date	Nov 22, 2013
Publication date	May 28, 2015
Grant date	—

Abstract

The present invention provides a display device and a dual gate type thin film transistor (TFT) structure for an electronic device. According to an embodiment, the dual gate TFT structure includes a first gate electrode formed on a substrate; a semiconductor layer formed on the first gate electrode; an insulating layer formed on the semiconductor layer, and including first, second and third contact holes therein; drain and source electrodes in contact with the semiconductor layer respectively through the first and second contact holes; a passivation layer formed on the drain electrode and the source electrode, and including a fourth contact hole therein; a planarization layer formed on the passivation layer, and including a fifth contact hole therein; and a second gate electrode formed on the planarization layer, and in electrical contact with the first gate electrode through the third, fourth and fifth contact holes.

First claim

What is claimed is:

1 . A display device comprising:
a first gate electrode and a gate insulating layer both formed on a substrate; a semiconductor layer formed on the gate insulating layer; an etch stopper formed on the gate insulating layer, and including first, second and third contact holes therein; a drain electrode and a source electrode both formed on the etch stopper, and both in contact with the semiconductor layer respectively through the first and second contact holes; a first auxiliary pattern in contact with the first gate electrode through the third contact hole; a passivation layer formed on the drain electrode and the source electrode, and including a fourth contact hole therein; a second auxiliary pattern in contact with the first auxiliary pattern through the fourth contact hole; a planarization layer formed on the passivation layer and the second auxiliary pattern, and including a fifth contact hole herein; and a second gate electrode formed on the planarization layer, and in contact with the second auxiliary pattern through the fifth contact hole.

2 . The display device of claim 1 , further comprising:
an electrode layer formed on the planarization layer and being adjacent to the second gate electrode, wherein the second gate electrode and the electrode layer are formed with a same material.

3 . The display device of claim 1 , wherein the second gate electrode is separated from the passivation layer by the planarization layer formed between the second gate electrode and the passivation layer.

4 . The display device of claim 1 , wherein the first auxiliary pattern, the second auxiliary pattern and the second gate electrode are stacked on top of each other on the first gate electrode in the third, fourth and fifth contact holes.

5 . The display device of claim 1 , further comprising:
an auxiliary drain electrode formed on the passivation layer, and in contact with the drain electrode through the planarization layer.

6 . The display device of claim 5 , further comprising:
an organic light emitting diode (OLED) structure in electrical contact with the drain electrode through the auxiliary drain electrode.

7 . The display device of claim 6 , wherein the OLED structure includes:
a first electrode formed on the planarization layer, and in contact with the auxiliary drain electrode through the planarization layer; an organic emitting layer formed on the first electrode of the OLED structure; and a second electrode formed on the organic emitting layer.

8 . The display device of claim 1 , wherein the semiconductor layer further includes first and second semiconductor layer contact holes respectively formed below the first and second contact holes.

9 . The display device of claim 8 , wherein the drain electrode is in contact with the gate insulating layer through the first contact hole and the first semiconductor layer contact hole, and
the source electrode is in contact with the gate insulating layer through the second contact hole and the second semiconductor layer contact hole.

10 . The display device of claim 1 , further comprising:
a color filter pattern formed on the passivation layer and under the planarization layer.

11 . The display device of claim 10 , wherein the semiconductor layer further includes first and second semiconductor layer contact holes respectively formed below the first and second contact holes.

12 . The display device of claim 11 , wherein the drain electrode is in contact with the gate insulating layer through the first contact hole and the first semiconductor layer contact hole, and
the source electrode is in contact with the gate insulating layer through the second contact hole and the second semiconductor layer contact hole.

13 . A dual gate type thin film transistor (TFT) structure for an electronic device, the structure comprising:
a first gate electrode formed on a substrate; a semiconductor layer formed on the first gate electrode; an insulating layer formed on the semiconductor layer, and including first, second and third contact holes therein; drain and source electrodes in contact with the semiconductor layer respectively through the first and second contact holes; a passivation layer formed on the drain electrode and the source electrode, and including a fourth contact hole therein; a planarization layer formed on the passivation layer, and including a fifth contact hole therein; and a second gate electrode formed on the planarization layer, and in electrical contact with the first gate electrode through the third, fourth and fifth contact holes.

14 . The structure of claim 13 , further comprising:
an electrode layer formed on the planarization layer and being adjacent to the second gate electrode, wherein the second gate electrode and the electrode layer are formed with a same material.

15 . The structure of claim 13 , further comprising:
at least one auxiliary pattern formed in at least one of the third and fourth contact holes, and in contact with the first and second gate electrodes.

16 . The structure of claim 15 , wherein the at least one auxiliary pattern includes first and second auxiliary patterns, and
the first and second auxiliary patterns and the second gate electrode are stacked on top of each other on the first gate electrode in the third, fourth and fifth contact holes.

17 . The structure of claim 13 , wherein the second gate electrode is separated from the passivation layer by the planarization layer formed between the second gate electrode and the passivation layer.

18 . The structure of claim 13 , further comprising:
an auxiliary drain electrode formed on the passivation layer, and in contact with the drain electrode through the planarization layer.

19 . The structure of claim 13 , further comprising:
a gate insulating layer formed between the first gate electrode and the semiconductor layer, wherein the semiconductor layer further includes first and second semiconductor layer contact holes respectively formed below the first and second contact holes.

20 . The structure of claim 19 , wherein the drain electrode is in contact with the gate insulating layer through the first contact hole and the first semiconductor layer contact hole, and
the source electrode is in contact with the gate insulating layer through the second contact hole and the second semiconductor layer contact hole.

21 . The structure of claim 13 , further comprising:
a color filter pattern formed on the passivation layer and under the planarization layer.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Jeong-Hwan
• Cho Ki-Sul

Classifications

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/673 Primary

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title