Self-formation of high-density arrays of nanostructures
US-9324794-B2 · Apr 26, 2016 · US
Self-formation of high-density arrays of nanostructures
US2016204196A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016204196-A1 |
| Application number | US-201615077213-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 22, 2016 |
| Priority date | Mar 21, 2013 |
| Publication date | Jul 14, 2016 |
| Grant date | — |
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Abstract
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A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device, comprising: a crystalline semiconductor layer, the crystalline semiconductor layer being cracked to form parallel structures along at least one direction; and a two-dimensional material formed on the crystalline semiconductor layer being separated at cracks in the crystalline semiconductor layer to form nanostructures. 2 . The device as recited in claim 1 , wherein the cracks are spaced by an intercrack distance which is proportional to an applied strain during crack propagation. 3 . The device as recited in claim 1 , wherein the two-dimensional material includes graphene. 4 . The device as recited in claim 1 , wherein the crystalline semiconductor layer includes SiC. 5 . The device as recited in claim 1 , further comprising second cracks formed transversely to the cracks along the at least one direction. 6 . The device as recited in claim 5 , wherein the second cracks are formed through the crystalline semiconductor layer and through the two-dimensional material. 7 . The device as recited in claim 6 , wherein the second cracks in combination with first cracks provide dot structures including the two-dimensional material on the crystalline semiconductor layer. 8 . The device as recited in claim 1 , further comprising: an electronic or photonic device formed by incorporating the parallel structures.
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Classifications
Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title
Silicon carbide · CPC title
Carbon, e.g. diamond-like carbon · CPC title
- H10P14/38Primary
characterised by treatments done after the formation of the materials · CPC title
Manufacture or treatment of nanostructures · CPC title
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- What does patent US2016204196A1 cover?
- A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconducto…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10P14/38. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jul 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).