Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016190930-A1
Application number	US-201615065762-A
Country	US
Kind code	A1
Filing date	Mar 9, 2016
Priority date	Oct 23, 2012
Publication date	Jun 30, 2016
Grant date	—

Abstract

Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

First claim

1 - 8 . (canceled)

9 . A semiconductor device including a DC/DC converter circuit, the semiconductor device comprising:
a substrate; first, second, and third frames formed over the substrate; a compound semiconductor substrate formed over the substrate; a first transistor constituting a part of the DC/DC converter circuit and formed over the compound semiconductor substrate; and a second transistor constituting another part of the DC/DC converter circuit and formed over the compound semiconductor substrate, wherein the first transistor includes a first gate electrode, a first gate insulating film, a first source electrode, and a first drain electrode and is arranged between a first pad and a second pad in plan view, wherein the second transistor includes a second gate electrode, a second gate insulating film, a second source electrode, and a second drain electrode and is arranged between the second pad and a third pad in plan view, wherein the first drain electrode is connected to the first pad, wherein the first source electrode and the second drain electrode are connected to the second pad, wherein the second source electrode is connected to the third pad, wherein the first pad is connected to the first frame through a first clip, wherein the second pad is connected to the second frame through a second clip, and wherein the third pad is connected to the third frame through a third clip.

10 . The semiconductor device according to claim 9 , wherein the compound semiconductor substrate has a GaN layer and an AlGaN layer over the GaN layer.

11 . The semiconductor device according to claim 10 ,
wherein a part of the first gate electrode is disposed within a recess in the compound semiconductor substrate, and wherein the second gate electrode has a planar gate structure.

12 . The semiconductor device according to claim 11 ,
wherein the first transistor is a normally-off type transistor, and wherein the second transistor is a normally-on type transistor.

13 . The semiconductor device according to claim 10 , wherein each of the first, second, and third clips includes copper.

14 . The semiconductor device according to claim 13 , wherein the first, second, and third pads are bonded by solder to the first, second, and third clips, respectively.

Assignees

• Renesas Electronics Corp

Inventors

• Nega Ryohei
• Miura Yoshinao

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title