Semiconductor substrate and semiconductor package structure having the same

Patent metadata

Field	Value
Publication number	US-2016190079-A1
Application number	US-201414586735-A
Country	US
Kind code	A1
Filing date	Dec 30, 2014
Priority date	Dec 30, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

First claim

1 . A semiconductor package structure, comprising:
a substrate comprising:
an insulating layer having a top surface;
a conductive circuit layer recessed from the top surface of the insulating layer, wherein the conductive circuit layer comprises at least one pad and a trace, and the trace is exposed from the insulating layer; and
a conductive bump disposed on the at least one pad, wherein a side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space;
a semiconductor chip; and a conductive material electrically connecting the conductive bump and the semiconductor chip, wherein a portion of the conductive material is disposed in the accommodating space.

2 . The semiconductor package structure according to claim 1 , wherein a ratio of a width of the conductive bump to a width of the at least one pad is in the range of 0.5 to 0.8.

3 . The semiconductor package structure according to claim 1 , wherein the trace is disposed adjacent to the at least one pad, the semiconductor chip comprises an Under Bump Metal (UBM), and a side surface of the UBM is substantially coplanar with a side surface of the trace.

4 . The semiconductor package structure according to claim 1 , wherein the conductive bump is disposed within the circumference of the at least one pad.

5 . The semiconductor package structure according to claim 1 , wherein the conductive bump covers a portion of the insulating layer.

6 . The semiconductor package structure according to claim 1 , wherein a width of the accommodating space is greater than the difference between a width of the conductive bump and a width of the at least one pad.

7 . The semiconductor package structure according to claim 1 , wherein a width of the conductive bump is less than a width of the at least one pad.

8 . The semiconductor package structure according to claim 1 , wherein the at least one pad has a geometrical central axis, the conductive bump has a geometrical central axis, and there is an offset between the geometrical central axis of the at least one pad and the geometrical central axis of the conductive bump.

9 . The semiconductor package structure according to claim 1 , wherein the conductive bump comprises a main portion, a metal layer portion and a protrusion portion, the protrusion portion protrudes from the at least one pad, the metal layer portion is disposed on the protrusion portion, the main portion is disposed on the metal layer portion, and the widths of the main portion, the metal layer portion and the protrusion portion are substantially the same.

10 . The semiconductor package structure according to claim 9 , wherein the protrusion portion and the at least one pad are formed integrally.

11 . A semiconductor package structure, comprising:
a substrate comprising:
an insulating layer having a top surface;
a conductive circuit layer recessed from the top surface of the insulating layer, wherein the conductive circuit layer comprises at least one first pad and a trace, and the trace is exposed from the insulating laver; and
a first conductive bump disposed on the first pad;
a semiconductor chip; and a conductive material electrically connected to the first conductive bump and the semiconductor chip, wherein a part of the conductive material is lower than the top surface of the insulating layer.

12 . The semiconductor package structure according to claim 11 , wherein a width of the first conductive bump is less than a width of the first pad, and a side surface of the first conductive bump, a top surface of the first pad and a side surface of the insulating layer define a first accommodating space.

13 . The semiconductor package structure according to claim 11 , wherein a ratio of a width of the first conductive bump to a width of the first pad is in a range from 0.5 to 0.8.

14 . The semiconductor package structure according to claim 11 , wherein the substrate further comprises a second conductive bump, and the conductive circuit layer further comprises a second pad, wherein the second conductive bump is disposed on the second pad, a width of the second conductive bump is less than a width of the second pad, a side surface of the second conductive bump, a top surface of the second pad and a side surface of the insulating layer define a second accommodating space, and the trace is disposed between the first pad and the second pad.

15 . The semiconductor package structure according to claim 11 , wherein the first conductive bump is positioned within a circumference of the first pad.

16 . The semiconductor package structure according to claim 11 , wherein the first conductive bump covers a portion of the insulating layer.

17 . The semiconductor package structure according to claim 11 , wherein a width of the first conductive bump is less than a width of the first pad.

18 . The semiconductor package structure according to claim 11 , wherein the first pad has a geometrical central axis, the first conductive bump has a geometrical central axis, and there is an offset between the geometrical central axis of the first pad and the geometrical central axis of the first conductive bump.

19 . The semiconductor package structure according to claim 11 , wherein the first conductive bump comprises a main portion, a metal layer portion and a protrusion portion, the protrusion portion protrudes from the first pad, the metal layer portion is disposed on the protrusion portion, the main portion is disposed on the metal layer portion, and the widths of the main portion, the metal layer portion and the protrusion portion are substantially the same.

20 . The semiconductor package structure according to claim 19 , wherein the protrusion portion and the first pad are formed integrally.

Assignees

• Advanced Semiconductor Eng

Inventors

• Liao Guo-Cheng
• Chen Chia-Ching
• Ding Yi-Chuan

Classifications

• H05K3/4682

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K2201/10674

  Flip chip · CPC title

• H05K3/205

  using a pattern electroplated or electroformed on a metallic carrier · CPC title

• H05K2201/10378

  Interposers · CPC title

• H05K2201/09509

  Blind vias, i.e. vias having one side closed · CPC title