Interconnect structure for molded ic packages

Patent metadata

Field	Value
Publication number	US-2016190057-A1
Application number	US-201615061747-A
Country	US
Kind code	A1
Filing date	Mar 4, 2016
Priority date	Jun 17, 2013
Publication date	Jun 30, 2016
Grant date	—

Abstract

Various examples are provided for interconnection structures for molded IC packages. In one example, among others, an IC package includes a substrate and an interposer. A plurality of conductive elements provide physical and electrical contact between a surface of the substrate and a surface of the interposer. A standoff element disposed between the surfaces of the substrate and interposer provides a minimum spacing between the surfaces of the substrate and interposer. In some implementations, a standoff element is disposed between an IC die disposed on the surface of the substrate and the surface of the interposer. In another example, a method includes coupling conductive elements to a surface of an interposer, attaching a standoff element, coupling the conductive elements to a surface of a substrate, and forming an embedded layer between the interposer and substrate. The standoff element defines a minimum gap between the interposer and the substrate.

First claim

1 . An integrated circuit (IC) package, comprising:
a substrate including a first surface and a second surface opposite the first surface of the substrate; an interposer including a first surface and a second surface opposite the first surface of the interposer; a plurality of homogeneous solder balls disposed between the first surface of the substrate and the second surface of the interposer, the plurality of homogeneous solder balls providing physical and electrical contact between the substrate and the interposer; an IC die disposed on the first surface of the substrate; and a standoff element disposed between the IC die and the second surface of the interposer, the standoff element providing a predefined minimum spacing between the IC die and the second surface of the interposer.

2 . The IC package of claim 1 , wherein the standoff element is a standoff post comprising dummy silicon.

3 . The IC package of claim 2 , wherein the standoff post is attached to the second surface of the interposer.

4 . The IC package of claim 2 , wherein the standoff post is attached to a surface of the IC die.

5 . The IC package of claim 1 , wherein the standoff element is a solder mask attached to the second surface of the interposer.

6 . The IC package of claim 1 , wherein the standoff element is a passive element attached to the second surface of the interposer.

7 . The IC package of claim 1 , further comprising an embedded layer disposed between and in contact with the first surface of the substrate and the second surface of the interposer, the embedded layer encapsulating the plurality of homogeneous solder balls, the IC die, and at least a portion of the standoff element.

8 . The IC package of claim 1 , wherein the standoff element is centered over the IC die.

9 . The IC package of claim 1 , wherein the standoff element includes a plurality of standoff posts disposed between the IC die and the second surface of the interposer.

10 . The IC package of claim 1 , wherein a die attach material is used to affix the standoff element to the IC die.

11 . The IC package of claim 1 , wherein the standoff element is a solder mask that protrudes from the second surface of the interposer.

12 . The IC package of claim 6 , wherein an insulating layer is disposed between the passive element and the IC die.

13 . The IC package of claim 6 , wherein the passive element is one of a capacitor or a resistor.

14 . The IC package of claim 1 , wherein a plurality of conductive regions are disposed on the first surface of the substrate, the second surface of the substrate, the first surface of the interposer, and the second surface of the interposer.

15 . The IC package of claim 1 , wherein a plurality of conductive elements are disposed on an outer surface of the second surface of the substrate.

16 . The IC package of claim 1 , wherein the IC die is disposed on a plurality of conductive elements that contact the first surface of the substrate.

17 . The IC package of claim 1 , wherein the IC die includes one of a processor or an application specific integrated circuit (ASIC).

18 . The IC package of claim 14 , wherein the plurality of conductive regions include east one of a ball pad or a bump pad.

19 . An integrated circuit (IC) package, comprising:
a substrate including a first surface and a second surface opposite the first surface of the substrate; an interposer including a first surface and a second surface opposite the first surface of the interposer; an IC die disposed on the first surface of the substrate; and a standoff element disposed between the IC die and the second surface of the interposer.

20 . An integrated circuit (IC) package, comprising:
a substrate; an interposer; an IC die disposed on the substrate; and a standoff element disposed between the IC die and the interposer.

Assignees

• Broadcom Corp

Inventors

• Zhao Sam Ziqun
• Khan Rezaur Rahman

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/248

  for antennas · CPC title