Through-Substrate Vias with Improved Connections

Patent metadata

Field	Value
Publication number	US-2016181179-A1
Application number	US-201615056935-A
Country	US
Kind code	A1
Filing date	Feb 29, 2016
Priority date	Apr 28, 2010
Publication date	Jun 23, 2016
Grant date	—

Abstract

A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

First claim

What is claimed is:

1 . A method of manufacturing a device, the method comprising:
etching a first opening in a dielectric structure, the dielectric structure comprising a plurality of metallization layers formed in a plurality of respective dielectric layers, wherein the first opening exposes a metal pad disposed in at least one of the plurality of dielectric layers; etching a second opening through the dielectric structure and into a portion of a substrate disposed below the dielectric structure, wherein the etching the first opening and the etching the second opening occur simultaneously; and simultaneously filling the first opening and the second opening with a conductive material.

2 . The method of claim 1 , further comprising grinding a backside of the substrate to expose the conductive material within the second opening.

3 . The method of claim 1 , further comprising forming a conductive line interconnecting the conductive material within the first opening and the conductive material within the second opening.

4 . The method of claim 3 , wherein the conductive line is formed in a same step as the step of simultaneously filling the first opening and the second opening.

5 . The method of claim 1 , further comprising:
overfilling the first opening and the second opening with the conductive material; and planarizing the overfilled conductive material to form a first conductive via in the first opening and a second conductive via in the second opening.

6 . The method of claim 5 , further comprising:
forming a trench in a dielectric material above the conductive material within the first opening and the conductive material within the second opening; lining the trench with a barrier material; and filling the line trench with a second conductive material.

7 . The method of claim 6 , wherein the second conductive material is a same material as the conductive material.

8 . The method of claim 1 , wherein the first opening has a first width, when viewed in cross section, and the second opening has a second width, when viewed in cross section, and the second width is wider than the first width.

9 . The method of claim 8 , wherein the first width is preselected and the second width is preselected such that the first opening extends a first depth and the second opening extends a second depth, greater than the first depth during a common etch process.

10 . A method of manufacturing a device, the method comprising:
forming a interconnect structure over a substrate, the interconnect structure including a plurality of conductive pads formed in respective dielectric layers of a plurality of dielectric layers; etching a first opening aligned with a first conductive pad, the first opening having a first width; simultaneously with etching the first opening, etching a second opening that extends at least partially through the substrate, the second opening have a second width greater than the first width; and simultaneously forming a first conductive via in the first opening and a second conductive via in the second opening.

11 . The method of claim 10 , wherein the first width and the second width are preselected such that the first opening extends to the first conductive pad at substantially the same time the second opening extends to at least partially through the substrate using the same process parameters.

12 . The method of claim 10 , wherein simultaneously forming a first conductive via in the first opening and a second conductive via in the second opening includes:
lining sidewalls of the first opening and the second opening with an insulating layer; lining the first opening and the second opening with a diffusion barrier; and filling the lined first opening and the lined second opening with a conductive material to form a first conductive via and a second conductive via, respectively.

13 . The method of claim 10 , further comprising forming an interconnection between the first conductive via and the second conductive via.

14 . The method of claim 13 , wherein forming an interconnection comprises:
forming a trench in a dielectric material above the conductive material within the first opening and the conductive material within the second opening; lining the trench with a barrier material; and filling the line trench with a second conductive material.

15 . The method of claim 10 , further comprising simultaneously with etching the first opening and the second opening, etching a third opening aligned with a second conductive pad, the second conductive pad being an a different dielectric layer than the first conductive pad, the third opening having a third width less than the first width.

16 . The method of claim 10 , further comprising:
overfilling the first opening and the second opening with the conductive material; and planarizing the overfilled conductive material to form the first conductive via in the first opening and the second conductive via in the second opening.

17 . A device comprising:
a substrate; an interconnect structure over the substrate, the interconnect structure comprising:
a plurality of low-k dielectric layers;
a plurality of metallization layers in the plurality of low-k dielectric layers and comprising metal pads, wherein the metal pads comprises copper; and
a dielectric layer over the plurality of metallization layers, wherein a k value of the dielectric layer is higher than k values of the plurality of low-k dielectric layers;
a through-substrate via (TSV) extending from a top surface of the dielectric layer to a bottom surface of the substrate; a first deep conductive via extending from the top surface of the dielectric layer to land on a first metal pad in a first one of the plurality of metallization layers; a second deep conductive via extending from the top surface of the dielectric layer to land on a second metal pad in a second one of the plurality of metallization layers different from the first one; and a metal line over the dielectric layer and electrically coupling the TSV to the first and the second deep conductive vias.

18 . The device of claim 17 , wherein the dielectric layer is formed of a non-low-k dielectric material.

19 . The device of claim 17 , wherein the TSV and the first and the second deep conductive vias form a continuous region with no diffusion barrier layer separating the TSV from the first and the second deep conductive vias.

20 . The device of claim 17 , wherein:
the first deep conductive via has a first width when viewed from cross section and a first height extending from topmost surface to bottommost surface of the first conductive via; the second deep conductive via has a second width when viewed from cross section and a second height extending from topmost surface to bottommost surface of the second conductive via; the TSV has a third width when viewed from cross section and a third height extending from topmost surface to bottommost surface of the TSV; the third width is greater than the second width and the first width and the third height is greater than the second height and the first height; and the second width is greater than the first width and the second height is greater than the first height.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lin Jing-Cheng
• Yang Ku-Feng

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title