Self-testing integrated circuits

Patent metadata

Field	Value
Publication number	US-9178684-B2
Application number	US-201414201370-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 7, 2013
Publication date	Nov 3, 2015
Grant date	Nov 3, 2015

Abstract

In an example, a self-testing integrated circuit (IC) includes N channels i and a controller, where i is an integer from 1 to N. Each channel i may include a clock and data recovery circuit (CDR), a pseudorandom bit stream (PRBS) generator circuit, and a PRBS checker and eye quality monitor (EQM) circuit. The controller may be configured to selectively couple the channels i in a daisy chain during self-testing.

First claim

What is claimed is:

1. A method of self-testing an integrated circuit (IC) that includes N channels i, where i is an integer from 1 to N, the method comprising:
selectively coupling the channels i in a daisy chain;
receiving a reference clock signal at a first clock and data recovery circuit (CDR) included in channel 1 ;
verifying, by the first CDR, CDR functionality of the first CDR using the reference clock signal;
generating, by a first pseudorandom bit stream (PRBS) gen…

Assignees

• Finisar Corp

Inventors

• Nguyen The Linh

Classifications

• G01R31/31727

  Physics · mapped topic

• H04L7/0008 Primary

  Electricity · mapped topic

• H04L7/0083

  Electricity · mapped topic

• G01R31/3187 Primary

  Physics · mapped topic