Minimization of bias temperature instability (bti) degradation in circuits

Patent metadata

Field	Value
Publication number	US-2016164497-A1
Application number	US-201414560109-A
Country	US
Kind code	A1
Filing date	Dec 4, 2014
Priority date	Dec 4, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.

First claim

What is claimed is:

1 . A circuit structure, comprising:
a first pfet device; a first nfet device connected to the pfet device; a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state; and a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.

2 . The circuit structure of claim 1 , wherein the keeper nfet device is on and active to preserve operating state and degradation of the keeper nfet device.

3 . The circuit structure of claim 1 , wherein the keeper pfet device is on and active preserve operating state and degradation of the keeper pfet device.

4 . The circuit structure according to claim 1 , wherein the associated first nfet device operates in relaxation mode, once stress of the first nfet is reduced.

5 . The circuit structure according to claim 1 , wherein the associated first pfet device operates in relaxation mode, once stress of the first pfet device is reduced.

6 . The circuit structure according to claim 1 , wherein stress of the associated first nfet device is based on negative bias temperature instability of the circuit structure.

7 . The circuit structure according to claim 6 , wherein the negative bias temperature instability exhibits an increase in non-mobile negative charge during stress of the circuit structure.

8 . The circuit structure according to claim 1 , wherein stress of the associated first pfet device is based on negative bias temperature instability of the circuit structure.

9 . The circuit structure according to claim 1 , wherein stress of the associated first pfet device is based on positive bias temperature instability of the circuit structure.

10 . The circuit structure according to claim 9 , wherein the negative bias temperature instability exhibits an increase in non-mobile positive charge during stress of the circuit structure.

11 . A method for minimizing bias temperature instability degradation of integrated circuits, the method comprising:
providing a first pfet device; providing a first nfet device connected to the pfet device; providing a keeper nfet device for reducing stress associated with the first nfet device by keeping the first nfet device off during its functional state; and providing a keeper pfet device for reducing stress associated with the first pfet device by keeping the first pfet device off during its functional state.

12 . The method according to claim 11 , wherein the keeper nfet device is on and active to preserve operating state and degradation of the keeper nfet device.

13 . The method according to claim 11 , wherein the keeper pfet device is on and active preserve operating state and degradation of the keeper pfet device.

14 . The method according to claim 11 , wherein the associated first nfet device operates in relaxation mode, once stress of the first nfet is reduced.

15 . The method according to claim 11 , wherein the associated first pfet device operates in relaxation mode, once stress of the first pfet device is reduced.

16 . The method according to claim 11 , wherein stress of the associated first nfet device is based on negative bias temperature instability of the circuit structure.

17 . The method according to claim 16 , wherein the negative bias temperature instability exhibits an increase in non-mobile negative charge during stress of the circuit structure.

18 . The method according to claim 11 , wherein stress of the associated first pfet device is based on negative bias temperature instability of the circuit structure.

19 . The method according to claim 11 , wherein stress of the associated first pfet device is based on positive bias temperature instability of the circuit structure.

20 . The method according to claim 19 , wherein the negative bias temperature instability exhibits an increase in non-mobile positive charge during stress of the circuit structure.

Assignees

• IBM

Inventors

• Agarwal Navin
• Arsovski Igor
• Bringivijayaraghavan Venkatraghavan
• Rengarajan Krishnan S

Classifications

• H10D89/811

  using FETs as protective elements · CPC title

• H03K19/00369

  Modifications for compensating variations of temperature, supply voltage or other physical parameters · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K3/011 Primary

  Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title

• H01L27/092

  Electricity · mapped topic