Chip-Resistor Manufacturing Method

Patent metadata

Field	Value
Publication number	US-2016163433-A1
Application number	US-201414905459-A
Country	US
Kind code	A1
Filing date	Jul 9, 2014
Priority date	Jul 17, 2013
Publication date	Jun 9, 2016
Grant date	—

Abstract

The invention is to provide a chip-resistor manufacturing method in which chipping can be restrained from occurring in an intersection portion between each primary segmentation groove and each secondary segmentation groove. Primary segmentation grooves 21 each having an uneven depth are formed in one surface of a large substrate 20 . Pairs of surface electrodes 3 extending across the primary segmentation grooves 21 , resistive elements 5 each striding between the surface electrodes 3 paired with each other, etc. are formed in the one surface of the large substrate 20 . Then, primary segmentation is performed on the large substrate 20 along the primary segmentation grooves 21 so as to open the surface side where the surface electrodes 3 , the resistive elements 5 , etc. are formed. Thus, a plurality of strip-like substrates 30 are obtained from the large substrate 20 . During the primary segmentation, each primary segmentation groove 21 begins to break from electrode formation regions which are small in groove depth but strong, and then breaks in intersection portions which are large in groove depth but brittle. Accordingly, it is possible to perform primary segmentation on the primary segmentation groove 21 without applying a large load to the intersection portions which are low in strength. Thus, it is possible to prevent chipping from occurring in the intersection portions.

First claim

1 . A chip-resistor manufacturing method, comprising: a step of forming primary segmentation grooves and secondary segmentation grooves in a sheet-like large substrate to thereby extend the primary segmentation grooves and the secondary segmentation grooves longitudinally and laterally; a step of forming pairs of electrodes in one surface of the large substrate to thereby extend the electrodes across the primary segmentation grooves; a step of forming resistive elements to thereby connect the resistive elements to the pairs of electrodes; a step of forming a protective layer to thereby cover the resistive elements with the protective layer; a step of segmenting the large substrate along the primary segmentation grooves to thereby form strip-like substrates; a step of forming end face electrodes on segmentation faces of the strip-like substrates; and a step of segmenting the strip-like substrates along the secondary segmentation grooves to thereby form individual devices; wherein:
of the primary segmentation grooves, regions which include intersection portions with the secondary segmentation grooves and in which the electrodes are not formed are set to be larger in groove depth than regions in which the electrodes are formed, so that the large substrate can be segmented along the primary segmentation grooves to thereby form the strip-like substrates.

2 . A chip-resistor manufacturing method according to claim 1 , wherein: the relation D 1 ≧(D 2 +20 μm) is established between D 1 and D 2 when the groove depth in the regions where the electrodes are not formed is D 1 and the groove depth in the regions where the electrodes are formed is D 2 .

3 . A chip-resistor manufacturing method according to claim 1 , wherein: the electrodes are formed with a film thickness of 30 μm to 60 μm on the large substrate, and the large substrate is then irradiated with a laser so that the primary segmentation grooves can be formed in the large substrate to extend across the electrodes.

4 . A chip-resistor manufacturing method according to claim 2 , wherein: the electrodes are formed with a film thickness of 30 μm to 60 μm on the large substrate, and the large substrate is then irradiated with a laser so that the primary segmentation grooves can be formed in the large substrate to extend across the electrodes.

Assignees

• Koa Corp

Inventors

• TAKEUE Yuya
• Uegane Todaro
• Matsumoto Kentaro

Classifications

• H01C17/06

  adapted for coating resistive material on a base · CPC title

• H01C17/28 Primary

  adapted for applying terminals · CPC title

• H01C17/22

  adapted for trimming · CPC title

• H01C17/242

  by laser · CPC title

• H01C17/006

  adapted for manufacturing resistor chips · CPC title