Method of forming strained structures of semiconductor devices

Patent metadata

Field	Value
Publication number	US-2016155801-A1
Application number	US-201615005628-A
Country	US
Kind code	A1
Filing date	Jan 25, 2016
Priority date	Nov 15, 2011
Publication date	Jun 2, 2016
Grant date	—

Abstract

A method of fabricating a semiconductor device comprises providing a substrate with a shallow trench isolation (STI) within the substrate and a gate stack. A cavity is formed between the gate stack and the STI. The cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate. A film is grown in the cavity and thereafter an opening formed by removing a first portion of the strained film until exposing the bottom surface of the substrate while a second portion of the strained film adjoins the STI sidewall. Another epitaxial layer is then grown in the opening.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, comprising:
providing a substrate comprising a major surface; forming a shallow trench isolation (STI) within the substrate; forming a gate stack on the major surface of the substrate, wherein the STI is disposed on one side of the gate stack; forming a cavity distributed between the gate stack and the STI, wherein the cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate; epitaxially growing a strained film in the cavity; forming an opening by removing a first portion of the strained film until exposing the bottom surface of the substrate, wherein a second portion of the strained film adjoins the STI sidewall; and epitaxially growing a SiGe layer in the opening.

2 . The method of claim 1 further comprising:
forming a dummy gate stack with a sidewall spacer over the STI; and
forming a recess in the STI below the sidewall spacer.

3 . The method of claim 2 , wherein the step of forming a recess in the STI is performed by a wet etching process.

4 . The method of claim 3 , wherein a wet etch process is performed in a solution comprising HF.

5 . The method of claim 1 , wherein the step of forming the opening removes the strained film on the sidewall of the substrate.

6 . The method of claim 1 , wherein the step of forming the opening does not fully remove the strained film on the sidewall of the substrate.

7 . The method of claim 1 , wherein the forming the cavity distributed between the gate stack and the STI includes aligning the sidewall formed by the STI with a spacer element abutting the gate stack.

8 . The method of claim 1 , wherein the providing the major surface provides a top surface of a fin structure of the substrate.

9 . A method of fabricating a semiconductor device, comprising:
forming a shallow trench isolation (STI) within a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming a cavity in the semiconductor substrate between the gate stack and the STI; growing an epitaxial film in the cavity; defining an opening by etching a portion of the epitaxial film to expose a surface of the cavity defined by the semiconductor substrate, wherein after the etching the epitaxial film abuts a sidewall of the STI; and epitaxially growing a semiconductor layer in the opening.

10 . The method of claim 9 , wherein the forming the STI defines a fin structure on the semiconductor substrate; and
wherein the forming the gate stack provides forming the gate stack on at least at least on surface of the fin structure.

11 . The method of claim 10 , wherein the forming the cavity includes forming the cavity in the fin structure.

12 . The method of claim 9 , wherein the forming the cavity includes etching the semiconductor substrate and etching the STI.

13 . The method of claim 9 , wherein the forming the cavity includes using spacers abutting the gate stack as a hard mask during the forming the cavity.

14 . The method of claim 9 , wherein the growing the epitaxial film in the cavity includes epitaxially growing at least one of a II-VI semiconductor material and a III-V semiconductor material.

15 . A method of fabricating a semiconductor device, comprising:
forming a shallow trench isolation (STI) within a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming a cavity in the semiconductor substrate between the gate stack and the STI, wherein the forming the cavity includes removing a portion of the STI to form a recessed sidewall of the STI; growing an epitaxial film such that the epitaxial film is disposed on a sidewall of the cavity adjacent the STI; etching the epitaxial film to expose a bottom surface of the cavity defined by the semiconductor substrate, wherein after the etching the epitaxial film abuts the recessed sidewall of the STI; and epitaxially growing a semiconductor layer in the opening from the bottom surface of the cavity.

16 . The method of claim 15 , wherein the forming the cavity is performed by a wet etching process.

17 . The method of claim 15 , wherein the growing the epitaxial film includes growing at least one of a II-VI semiconductor material and a III-V semiconductor material.

18 . The method of claim 17 , wherein the growing the epitaxial film is performed by a metal-organic chemical vapor deposition (MOCVD) process.

19 . The method of claim 15 , where the etching the epitaxial film to expose the bottom surface of the cavity also exposes a sidewall of the cavity opposite the STI.

20 . The method of claim 15 , wherein the etching the epitaxial film is performed by a reactive ion etch (RIE).

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10D30/797 Primary

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/0275

  forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions · CPC title

• H10D62/82

  Heterojunctions · CPC title