Process based metrology target design

Patent metadata

Field	Value
Publication number	US-2016140267-A1
Application number	US-201514941347-A
Country	US
Kind code	A1
Filing date	Nov 13, 2015
Priority date	Nov 17, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.

First claim

What is claimed is:

1 . A method of designing a metrology target in a simulation domain, the metrology target compatible to a lithography process used to fabricate a physical device on a substrate, the method comprising:
providing design parameters for generating a metrology target; designing, by a computer apparatus, a three-dimensional geometrical structure of the metrology target based on a model of the lithography process and the design parameters for the metrology target, wherein the model of the lithography process represents a sequence of process steps; and visually rendering a gradual formation of the three-dimensional geometric structure of the metrology target at substrate level in the simulation domain.

2 . The method of claim 1 , wherein the design of the metrology target is automated.

3 . The method of claim 2 , wherein a plurality of metrology targets is designed automatically.

4 . The method of claim 3 , wherein the method further comprises:
perturbing a parameter of a process step within the sequence of process steps; applying the process step with the perturbed parameter to the designed plurality of metrology targets; selecting a subset of metrology targets from the designed plurality of metrology targets for which the change in the three-dimensional geometric structure is minimal when the process step with the perturbed parameter is applied.

5 . The method of claim 3 , wherein the device comprises multiple device layers.

6 . The method of claim 5 , wherein each device layer corresponds to a respective sequence of process steps in the overall model of the lithography process.

7 . The method of claim 5 , wherein the metrology target comprises a multi-layer configuration corresponding to at least some of the multiple device layers of the device.

8 . The method of claim 7 , wherein at least one of the design parameters used for generating the metrology target comprises a parameter indicating overlay between two device layers of the device.

9 . The method of claim 7 , wherein a relationship between two distinct features of a metrology target is provided as a design parameter, such that if one of the distinct features is altered, the other is also automatically altered.

10 . The method of claim 9 , wherein the two distinct features belong to two different device layers.

11 . The method of claim 3 , wherein each process step is assigned respective process step indicia.

12 . The method of claim 11 , wherein each designed metrology target is tagged with the process step indicia to facilitate retrieval of particular designs from a metrology target database containing a plurality of designed metrology targets.

13 . The method of claim 1 , wherein individual process steps include one or more selected from: deposition, photoresist coating, patterning, etching, stripping, and/or planarization.

14 . The method of claim 1 , wherein feature dimensions of the metrology target vary during individual process steps reflecting process-induced effects on a post-processed substrate structure.

15 . The method of claim 1 , wherein materials used for individual process steps are selected from a material library.

16 . The method of claim 15 , wherein the model for the lithography process provides run time estimation of the simulation process once the materials, the individual process steps, and the design parameters of the metrology targets are provided.

17 . The method of claim 1 , further comprising, through a viewing editor, providing a user various tools for visualization, the tools including one or more selected from: coloring, shading, rotating, slicing, making device layers transparent, zooming in, and/or zooming out.

18 . A computer program product comprising a non-transitory computer readable medium having instructions recorded thereon, the instructions when executed by a computer implementing the method of claim 1 .

Assignees

• Asml Netherlands Bv

Inventors

• Chen Guangqing
• Bai Shufeng
• Kent Eric Richard
• Lu Yen-Wen
• Tuffy Paul Anthony
• Wang Jen-Shiang
• Zhang Youping
• Zwartjes Gertjan
• Bijlsma Jan Wouter

Classifications

• G03F7/705 Primary

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title

• G03F7/70633

  Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G03F7/70683

  Mark designs · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title