Signal transmitting device, signal transmitting/receiving device, and image display device

Patent metadata

Field	Value
Publication number	US-2016127615-A1
Application number	US-201514887112-A
Country	US
Kind code	A1
Filing date	Oct 19, 2015
Priority date	Oct 31, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

The signal transmitting device of a signal transmitting/receiving device according to the present disclosure includes a signal processing unit that outputs a video signal as parallel data together with the first clock (the pixel clock); a first buffer memory to which the parallel data is written based on the first clock from the signal processing unit, and from which the written parallel data is read based on the second clock having a constant frequency equal to or higher than that of the first clock; and a transmitting unit. The transmitting unit receives the parallel data read from the first buffer memory and the second clock, converts the parallel data into serial data, and outputs the serial data to the signal line based on the second clock. The first buffer memory and the transmitting unit are formed of an FPGA (field-programmable gate array).

First claim

What is claimed is:

1 . A signal transmitting device comprising:
a signal processing unit that outputs a video signal in a form of parallel data along with a first clock as a pixel clock; a first buffer memory to which the parallel data is written based on the first clock from the signal processing unit, and from which the written parallel data is read based on a second clock having a constant frequency equal to or higher than that of the first clock; and a transmitting unit that receives the parallel data read from the first buffer memory and the second clock, converts the parallel data into serial data, and outputs the serial data to a signal line based on the second clock, wherein the first buffer memory and the transmitting unit are formed of an FPGA (field-programmable gate array).

2 . The signal transmitting device of claim 1 , further comprising a clock generator generating the second clock, wherein the first buffer memory, the transmitting unit, and the clock generator are formed of an FPGA.

3 . The signal transmitting device of claim 1 , wherein the signal processing unit, the first buffer memory, and the transmitting unit are formed of an FPGA.

4 . A signal transmitting/receiving device comprising a signal transmitting device of claim 1 and a signal receiving device, wherein the signal receiving device includes:
a receiver that receives serial data from the transmitting unit together with the second clock through the signal line, converts the serial data to the parallel data, and outputs the parallel data together with the second clock; and
a second buffer memory to which the parallel data is written based on the second clock, and from which the written parallel data is read based on the first clock, and

wherein the second buffer memory and the receiver are formed of an FPGA.

5 . The signal transmitting/receiving device of claim 4 ,
wherein the first buffer memory and the second buffer memory are FIFO (first in first out) memories, and wherein the transmitting unit transmits an LVDS (low voltage differential signaling) signal to the receiver.

6 . An image display device comprising the signal transmitting/receiving device of claim 4 and a display device.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Ikeuchi Nobuo

Classifications

• H04N5/38

  Transmitter circuitry {for the transmission of television signals according to analogue transmission standards} (H04N5/14 takes precedence) · CPC title

• H04N5/067 Primary

  Arrangements or circuits at the transmitter end · CPC title

• G09G2370/14

  Use of low voltage differential signaling [LVDS] for display data communication · CPC title

• H04N21/242

  Synchronisation processes, e.g. processing of PCR [Programme Clock References] {(arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18)} · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title