Optoelectronic ball grid array package with fiber

US2016124164A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016124164-A1
Application numberUS-201514927016-A
CountryUS
Kind codeA1
Filing dateOct 29, 2015
Priority dateOct 29, 2014
Publication dateMay 5, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A photonic integrated circuit may be coupled to an optical fiber and packaged. The optical fiber may be supported by a fiber holder during a solder reflow process performed to mount the packaged photonic integrated circuit to a circuit board or other substrate. The optical fiber may be decoupled from the fiber holder, and the fiber holder removed, after completion of the solder reflow process.

First claim

Opening claim text (preview).

What is claimed is: 1 . An apparatus, comprising: a substrate having a first surface; a photonic integrated circuit (PIC) coupled to the substrate and having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the PIC and distal the first surface of the substrate; a lid, contacting the first surface of the substrate; a fiber holder disposed on the lid; and an optical fiber coupled to the PIC and in contact with the fiber holder. 2 . The apparatus according to claim 1 , wherein a portion of the optical fiber is coiled around the fiber holder. 3 . The apparatus according to claim 2 , wherein the portion of the optical fiber is coiled around the fiber holder within a plane that is substantially parallel to the second surface of the PIC. 4 . The apparatus according to claim 1 , wherein the optical fiber is edge-coupled to the PIC. 5 . The apparatus according to claim 1 , further comprising an electronic integrated circuit disposed on the first surface of the substrate. 6 . The apparatus according to claim 1 , further comprising a circuit board on which the substrate in mounted. 7 . The apparatus according to claim 6 , wherein the substrate is electrically connected to the circuit board through a ball grid array. 8 . The apparatus according to claim 1 , wherein the fiber holder is made of copper. 9 . The apparatus according to claim 1 , further comprising an interposer having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the interposer and proximate the first surface of the PIC. 10 . The apparatus according to claim 1 , further comprising a fiber assembly containing a groove on which the optical fiber is disposed. 11 . The apparatus according to claim 10 , further comprising a thermal pad contacting the fiber assembly. 12 . A method, comprising: packaging a photonic integrated circuit (PIC) in a package comprising a substrate and a lid; mounting a fiber holder on the lid of the package such that the lid is between the PIC and the fiber holder; coupling an optical fiber to the PIC; mechanically coupling the optical fiber to the fiber holder. 13 . The method according to claim 12 , further comprising surface-mounting the package on a chip carrier. 14 . The method according to claim 13 , further comprising securing an end of the optical fiber on the fiber holder. 15 . The method according to claim 12 , further comprising performing reflow soldering of the package. 16 . The method according to claim 15 , further comprising removing the fiber holder from the package subsequent to the reflow soldering. 17 . The method according to claim 12 , wherein mechanically coupling the optical fiber to the fiber holder comprises coiling a portion of the optical fiber around the fiber holder. 18 . The method according to claim 17 , wherein the portion of the optical fiber is coiled around the fiber holder with a radius that is less than a minimum bend radius of the optical fiber. 19 . The method according to claim 12 , further comprising splicing the optical fiber to an optical component. 20 . The method according to claim 12 , wherein mounting the fiber holder on the lid of the package comprises mounting the fiber holder with at least one screw inserted on the lid. 21 . An apparatus, comprising: a substrate having a first surface; a photonic integrated circuit (PIC) coupled to the substrate and having a first surface proximate the first surface of the substrate and a second surface opposite the first surface of the PIC and distal the first surface of the substrate; a lid, contacting the first surface of the substrate and at least partially covering the PIC, exhibiting at least one retaining feature; and an optical fiber coupled to the PIC and in contact with the retaining feature of the lid. 22 . The apparatus of claim 21 , wherein the retaining feature comprises a groove in the lid. 23 . The apparatus of claim 21 , wherein the retaining feature comprises a fiber channel. 24 . The apparatus of claim 21 , wherein the lid is formed of a thermally conductive material.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • Bump connectors and die-attach connectors · CPC title

  • with heat insulation means to thermally decouple or restrain the heat from spreading · CPC title

  • G02B6/428Primary

    containing printed circuit boards [PCB] · CPC title

  • G02B6/423Primary

    using guiding surfaces for the alignment · CPC title

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Frequently asked questions

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What does patent US2016124164A1 cover?
A photonic integrated circuit may be coupled to an optical fiber and packaged. The optical fiber may be supported by a fiber holder during a solder reflow process performed to mount the packaged photonic integrated circuit to a circuit board or other substrate. The optical fiber may be decoupled from the fiber holder, and the fiber holder removed, after completion of the solder reflow process.
Who is the assignee on this patent?
Acacia Communications Inc
What technology area does this patent fall under?
Primary CPC classification G02B6/428. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu May 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).