Electronic and optical co-packaging of coherent transceiver

US9557478B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9557478-B2
Application numberUS-201314012876-A
CountryUS
Kind codeB2
Filing dateAug 28, 2013
Priority dateAug 28, 2012
Publication dateJan 31, 2017
Grant dateJan 31, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed herein are co-packaging structures, devices, and methods for integrating a photonic integrated circuit (PIC), an electronic integrated circuit including drivers and transimpedance amplifiers (TIAs) and an ASIC having analog-to-digital converters and a digital signal processor positioned on a common (the same) carrier thereby resulting in a compact coherent transceiver while lowering its cost.

First claim

Opening claim text (preview).

The invention claimed is: 1. A co-packaged electronic and optical apparatus comprising: a package substrate body; a chip comprising a driver and/or transimpedance amplifier (TIA), the chip being attached to the package substrate body; an application specific integrated circuit (ASIC) attached to and in electrical communication with the chip; a photonic integrated circuit (PIC) adjacent to and in electrical communication with the chip, the PIC having a surface; a single-piece mast positioned adjacent to the PIC; and an optical fiber coiled around the single-piece mast and having an end terminating substantially perpendicularly on the surface of the PIC. 2. The co-packaged electronic and optical apparatus of claim 1 , wherein the PIC and the ASIC are mechanically and electrically connected to the chip and a top surface of the package substrate body through the effect of ball grid array (BGA) structures. 3. The co-packaged electronic and optical apparatus of claim 2 , wherein a bottom surface of the package substrate body includes BGA structures. 4. The co-packaged electronic and optical apparatus of claim 2 , wherein the PIC includes a number of through silicon vias (TSVs) formed therein. 5. An apparatus comprising the co-packaged electronic and optical apparatus of claim 2 in combination with a laser source, wherein the PIC is optically connected to the laser source via the optical fiber. 6. A co-packaged apparatus comprising: a package substrate body; an interposer adjacent to and in electrical communication with the package substrate body through the effect of a ball grid array (BGA); a chip comprising a driver and/or transimpedance amplifier (TIA), the chip being adjacent to and in electrical communication with the interposer through the effect of a BGA; an application specific integrated circuit chip (ASIC) adjacent to and in electrical communication with the interposer through the effect of a BGA; a photonic integrated circuit (PIC) adjacent to and in electrical communication with the interposer through the effect of a BGA, wherein said interposer electrically interconnects the PIC to the chip and electrically interconnects the ASIC to the chip; a mast positioned adjacent to the PIC; and an optical fiber secured to the mast so that an end of the optical fiber is approximately normal to a surface of the PIC. 7. The co-packaged apparatus of claim 6 wherein a bottom surface of the package substrate body includes BGA structures. 8. The co-packaged apparatus of claim 7 , wherein the PIC includes a number of through silicon vias (TSVs) formed therein. 9. An apparatus comprising the co-packaged apparatus of claim 6 optically connected to a laser source via the optical fiber. 10. The apparatus of claim 5 , wherein the apparatus comprises an optical coherent transceiver of which the laser source and the co-packaged electronic and optical apparatus form a part. 11. The co-packaged electronic and optical apparatus of claim 1 , wherein the surface is a surface of a recess in the PIC, and wherein an optical fiber assembly is mounted in the recess. 12. The co-packaged electronic and optical apparatus of claim 11 , wherein the PIC is flip-chip mounted on the package substrate body. 13. The co-packaged electronic and optical apparatus of claim 12 , wherein the PIC further includes a mirror. 14. The co-packaged electronic and optical apparatus of claim 1 , wherein the chip is mounted in a recess of the package substrate body. 15. The co-packaged electronic and optical apparatus of claim 1 , wherein the surface is a backside surface of the PIC. 16. The apparatus of claim 9 , wherein the apparatus comprises an optical coherent transceiver of which the laser source and the co-packaged apparatus form a part. 17. The co-packaged apparatus of claim 6 , wherein the PIC includes an etched recess in which an optical fiber assembly is mounted to optically couple the optical fiber to the PIC. 18. The co-packaged apparatus of claim 6 , wherein the mast is mounted on the interposer.

Assignees

Inventors

Classifications

  • G02B6/428Primary

    containing printed circuit boards [PCB] · CPC title

  • G02B6/12Primary

    of the integrated circuit kind (electric integrated circuits H10B, H10D84/00 - H10D89/00, H10F19/00, H10F39/00, H10H29/00, H10K19/00, H10K39/00, H10K59/00, H10N19/00, H10N39/00, H10N59/00, H10N69/00, H10N79/00, H10N89/00) · CPC title

  • using guiding surfaces for the alignment · CPC title

  • Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections · CPC title

  • Combinations of two or more optical elements · CPC title

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Frequently asked questions

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What does patent US9557478B2 cover?
Disclosed herein are co-packaging structures, devices, and methods for integrating a photonic integrated circuit (PIC), an electronic integrated circuit including drivers and transimpedance amplifiers (TIAs) and an ASIC having analog-to-digital converters and a digital signal processor positioned on a common (the same) carrier thereby resulting in a compact coherent transceiver while lowering i…
Who is the assignee on this patent?
Acacia Communications Inc, Acacia Communications Inc
What technology area does this patent fall under?
Primary CPC classification G02B6/428. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).