Logic Compatible RRAM Structure and Process

Patent metadata

Field	Value
Publication number	US-2016118583-A1
Application number	US-201514985102-A
Country	US
Kind code	A1
Filing date	Dec 30, 2015
Priority date	Nov 12, 2012
Publication date	Apr 28, 2016
Grant date	—

Abstract

A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

First claim

What is claimed is:

1 . A method comprising:
forming a first dielectric layer having an opening over a first metal layer; forming a first electrode layer over the first dielectric layer and the first metal layer; forming a resistive layer over the first electrode layer; forming a second electrode layer over the resistive layer; patterning the second electrode layer to form a first lip portion that extends laterally over the resistive layer by a first distance beyond a region defined by the opening; patterning the resistive layer and the first electrode layer to form a second lip portion that extends laterally over the first dielectric layer by a second distance beyond the region defined by the opening, the second distance being different than the first distance; forming a second dielectric layer over the patterned second electrode layer; forming a trench extending through the second dielectric layer to the patterned second electrode layer; and forming a conductive material within the trench.

2 . The method of claim 1 , wherein the first lip portion is at a first height different from a second height of the second lip portion.

3 . The method of claim 1 , forming a spacer layer directly on the patterned second electrode layer and the resistive layer.

4 . The method of claim 1 , further comprising forming a third dielectric layer over the second electrode layer, and
wherein patterning the second electrode layer to form the first lip portion further includes patterning the third dielectric layer to form the first lip portion.

5 . The method of claim 4 , wherein forming the trench extending through the second dielectric to the patterned second electrode layer includes forming the trench through the third dielectric layer.

6 . The method of claim 1 , further comprising forming a second metal layer over the conductive material.

7 . The method of claim 1 , wherein forming the second dielectric layer over the patterned second electrode layer includes forming the second dielectric layer directly on the first dielectric layer such that the second dielectric layer physically contacts the first dielectric layer.

8 . A method comprising:
forming a first dielectric layer over a substrate having a first metal layer, the first dielectric layer defining an opening that exposes the first metal layer; forming a first electrode layer within the opening and over the first dielectric layer and the first metal layer; forming a second electrode layer over the first electrode layer; patterning the second electrode layer to form a first lip portion that extends laterally over the substrate by a first distance beyond a region defined by the opening; forming a spacer layer on the patterned second electrode layer; patterning the first electrode layer to form a second lip portion that extends laterally over the substrate by a second distance beyond the region defined by the opening, the second distance being different than the first distance; forming a second dielectric layer over the patterned second electrode layer; forming a trench extending through the second dielectric layer to the patterned second electrode layer; and forming a conductive material within the trench.

9 . The method of claim 8 , wherein the second distance is greater than the first distance.

10 . The method of claim 8 , further comprising forming a resistive layer over the first electrode layer, and
wherein forming the spacer layer on the patterned second electrode includes forming the spacer layer directly on the resistive layer such that the spacer layer physically contacts the resistive layer.

11 . The method of claim 10 , wherein patterning the first electrode layer to form the second lip portion includes patterning the resistive layer to form the second lip portion.

12 . The method of claim 11 , wherein patterning the resistive layer to form the second lip portion occurs after forming the spacer layer on the patterned second electrode.

13 . The method of claim 8 , wherein the first lip portion is at a first height different from a second height of the second lip portion.

14 . The method of claim 8 , wherein patterning the first electrode layer to form the second lip portion includes removing a portion of the first dielectric layer.

15 . The method of claim 8 , wherein forming the second dielectric layer over the patterned second electrode layer includes forming the second dielectric layer over the patterned first electrode layer such that the second dielectric layer physically contacts the patterned second electrode layer and the patterned first electrode layer.

16 . A method for forming a memory cell, the method comprising:
forming a substrate including a first metal layer; forming a first dielectric layer on the substrate; forming a conformal first electrode through a first opening in a first dielectric layer, the first opening being configured to allow physical contact between the first electrode and the first metal layer; forming a conformal resistive layer on the first electrode; forming a conformal spacing layer on the resistive layer; forming a conformal second electrode on the resistive layer; forming a conformal second dielectric layer on the second electrode, the second dielectric layer including a second opening; and coupling the second electrode to a second metal layer using a via that extends through the second opening; wherein:
the processes for forming the conformal first electrode and the conformal resistive layer include forming a first lip region that extends a first distance beyond a region defined by the first opening;
the processes for forming the conformal second electrode and the conformal second dielectric layer include forming a second lip region that extends a second distance beyond the region defined by the first opening; and
the process for forming the spacing layer includes forming the spacing layer on the resistive over the second lip region between the second distance and the first distance.

17 . The method of claim 16 , wherein the first lip region is at a first height different from a second height of the corresponding first electrode and the resistive layer located in the region defined by the first opening.

18 . The method of claim 17 , wherein the second lip region is at a third height different from the first height, the second height, and a fourth height of the corresponding second electrode and the second dielectric layer located in the region defined by the first opening.

19 . The method of claim 16 , wherein the second distance is shorter than the first distance.

20 . The method of claim 15 , wherein the processes for forming the conformal first electrode and the conformal second electrode do not include a chemical-mechanical polishing (CMP) process.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chang Chih-Yang
• Chen Hsia-Wei
• Yang Chin-Chieh
• Tu Kuo-Chi
• Chu Wen-Ting
• Liao yu-wen

Classifications

• H01L45/1253

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/1608 Primary

  Electricity · mapped topic

• H01L45/1666

  Electricity · mapped topic

• H10N70/841 Primary

  Electrodes · CPC title