High Mobility Devices with Anti-Punch Through Layer and Methods of Forming Same

Patent metadata

Field	Value
Publication number	US-2016104776-A1
Application number	US-201414555128-A
Country	US
Kind code	A1
Filing date	Nov 26, 2014
Priority date	Oct 10, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having APT dopants and a channel region over the APT layer. The channel region is substantially free of APT dopants. The semiconductor device further includes a conductive gate stack on a sidewall and a top surface of the channel region.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first fin extending upwards from a semiconductor substrate, wherein the first fin comprises:
a first anti-punch through (APT) layer comprising APT dopants; and
a first channel region over the first APT layer, wherein the first channel region is substantially free of APT dopants; and
a conductive gate stack on a sidewall and a top surface of the first channel region.

2 . The semiconductor device of claim 1 , wherein the first APT layer comprises silicon boron (SiB) or silicon carbon boron (SiCB).

3 . The semiconductor device of claim 1 , further comprising source and drain regions adjacent the conductive gate stack, wherein the first APT layer is disposed under the source and drain regions.

4 . The semiconductor device of claim 1 , further comprising a second fin extending upwards from the semiconductor substrate, wherein the second fin comprises:
a second APT layer comprising n-type APT dopants and p-type APT dopants; and a second channel region over the second APT layer.

5 . The semiconductor device of claim 4 , wherein a ratio of a first concentration of the p-type APT dopants in the second APT layer to a second concentration of the n-type APT dopants in the second APT layer is at least about two to one.

6 . The semiconductor device of claim 4 , wherein the second APT layer comprises silicon boron phosphorous or silicon carbon boron phosphorous.

7 . A semiconductor device comprising:
a first fin field effect transistor (finFET) comprising:
a first anti-punch through (APT) layer comprising first APT dopants of a first type; and
a first semiconductor layer over the first APT layer;
a first conductive gate stack on sidewalls and a top surface of the first semiconductor layer; and
first source and drain regions adjacent the first conductive gate stack; and
a second finFET comprising:
a second APT layer comprising second APT dopants of the first type and third APT dopants of a second type different than the first type;
a second semiconductor layer over the second APT layer;
a second conductive gate stack on sidewalls a top surface of the second semiconductor layer; and
second source and drain regions adjacent the second conductive gate stack.

8 . The semiconductor device of claim 7 , wherein the first semiconductor layer is substantially undoped with any APT dopants.

9 . The semiconductor device of claim 7 , wherein the first APT layer comprises silicon boron (SiB) or silicon carbon boron (SiCB), and wherein the second APT layer comprises silicon boron phosphorous (SiBP) or silicon carbon boron phosphorous (SiCBP).

10 . The semiconductor device of claim 7 , wherein second APT layer comprises at least about twice as many third APT dopants as second APT dopants.

11 . The semiconductor device of claim 7 , wherein the first finFET further comprises:
a third semiconductor layer under the first APT layer; and a semiconductor oxide layer on a sidewall of the third semiconductor layer.

12 . The semiconductor device of claim 7 , wherein the first APT layer is disposed under the first source and drain regions, and wherein the second APT layer is disposed under the second source and drain regions.

13 . A method for forming a semiconductor device, the method comprising:
forming an anti-punch through (APT) layer over a semiconductor substrate, wherein the APT layer comprises first APT dopants; forming a semiconductor layer over the APT layer; patterning the semiconductor layer and the APT layer to define a first fin extending upwards from the semiconductor substrate, wherein the first fin comprises a first APT layer portion and a first semiconductor layer portion; and forming a conductive gate stack on a top surface and a sidewall of the first semiconductor layer portion of the first fin.

14 . The method of claim 13 , wherein the semiconductor layer is substantially free of any APT dopants.

15 . The method of claim 13 , wherein patterning the semiconductor layer and the APT layer further defines a second fin comprising a second APT layer portion and a second semiconductor layer portion, and wherein the method further comprises:
removing the second semiconductor layer portion to expose the second APT layer portion; and implanting second APT dopants in the second APT layer portion, wherein the second APT dopants are of a different type than the first APT dopants.

16 . The method of claim 15 further comprising masking the first fin while implanting the second APT dopants.

17 . The method of claim 15 , wherein implanting the second APT dopants comprises implanting at least about twice as many of the second APT dopants as the first APT dopants in the second APT layer portion.

18 . The method of claim 15 , wherein the second APT layer portion comprises silicon boron phosphorous (SiBP) or silicon carbon boron phosphorous (SiCBP) after implanting the second APT dopants.

19 . The method of claim 13 , wherein forming the APT layer comprises epitaxially growing a layer comprising silicon boron or silicon carbon boron.

20 . The method of claim 13 further comprising forming source and drain regions in the first fin adjacent the conductive gate stack, wherein the first APT layer portion is disposed under the source and drain regions.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Ching Kuo-Cheng
• Fung Ka-Hing
• Wu Zhiqiang

Classifications

• H10D30/6215

  having multiple independently-addressable gate electrodes · CPC title

• H10D30/798

  being provided in or under the channel regions · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D62/371 Primary

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title

• H10D86/215

  comprising FinFETs · CPC title