Storage Module and Method for Datapath Bypass

Patent metadata

Field	Value
Publication number	US-2016103732-A1
Application number	US-201414510892-A
Country	US
Kind code	A1
Filing date	Oct 9, 2014
Priority date	Oct 9, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A storage module and method for datapath bypass are disclosed. In one embodiment, a storage module begins to perform a read operation that reads a set of code words from the memory and attempts to perform an error detection and correction operation on one of the read code words. In response to determining that the code word has an uncorrectable error, the storage module reads the other code words in the set but bypasses the error detection and correction operation on those other code words. The code word that had the uncorrectable error and the other code words are re-read, wherein at least the code word with the uncorrectable error is re-read with a different read condition. The storage module then attempts to perform the error detection and correction operation on the re-read code words. Other embodiments are provided.

First claim

What is claimed is:

1 . A method for datapath bypass, the method comprising:
performing the following in a storage module comprising a memory:
beginning to a perform a read operation that reads a set of code words from the memory;
attempting to perform an error detection and correction operation on a code word read from the memory; and
in response to determining that the code word has an uncorrectable error:
reading the other code words in the set but bypassing the error detection and correction operation on those other code words;
re-reading the code word that had the uncorrectable error and the other code words, wherein at least the code word with the uncorrectable error is re-read with a different read condition; and
attempting to perform the error detection and correction operation on the re-read code words.

2 . The method of claim 1 , wherein the storage module comprises at least one queue for storing instructions to read the set of code words from the memory, and wherein by reading the other code words in the set, the method avoids flushing the at least one queue in response to the uncorrectable error.

3 . The method of claim 1 , wherein the storage module is configured to perform at least one additional processing operation, and wherein the method further comprises bypassing the at least one additional processing operation in response to determining that the code word has an uncorrectable error.

4 . The method of claim 3 , wherein the at least one additional processing operation comprises a decryption operation.

5 . The method of claim 3 , wherein the storage module comprising a plurality of queues containing instructions to instruct components in the storage module to perform the at least one additional processing operation, and wherein the at least one additional processing operation is bypassed by setting a bypass command in the instructions.

6 . The method of claim 3 further comprising waiting until all the code words in the set have been read and additionally processed before releasing the set of code words as a response to a read command.

7 . The method of claim 1 , wherein the memory is a three-dimensional memory.

8 . The method of claim 1 , wherein the storage module is embedded in a host.

9 . The method of claim 1 , wherein the storage module is removably connected to a host.

10 . The method of claim 1 , wherein the storage module is a solid-state drive.

11 . A storage module comprising:
a memory; a data path comprising a plurality of components for processing a set of units of data read from the memory, wherein each component is associated with an instruction queue; and a context interface module configured to perform the following in response to an uncorrectable error occurring in one of the units of data read from the memory:
set a bypass command in the instruction queues for the components to bypass processing subsequent units of data in the set that are read from the memory;
re-read the unit of data that had the uncorrectable error and the subsequent units of data in the set, wherein at least the unit of data with the uncorrectable error is re-read with a different read condition; and
set a command in the instruction queues for the components to process the re-read units of data.

12 . The storage module of claim 11 , wherein the context interface module is further configured to wait until all the units of data have been re-read and processed before releasing any of the units of data as a response to a read command.

13 . The storage module of claim 11 , wherein the plurality of component in the data path comprise an error correction code engine and a decryption engine.

14 . The storage module of claim 11 , wherein the memory is a three-dimensional memory.

15 . The storage module of claim 11 , wherein the storage module is embedded in a host.

16 . The storage module of claim 11 , wherein the storage module is removably connected to a host.

17 . The storage module of claim 11 , wherein the storage module is a solid-state drive.

18 . A storage module comprising:
a memory; a first set of queues for storing instructions to read code words from the memory; a second set of queues for storing instructions to process code words from the memory; and a controller in communication with the memory and the first and second sets of queues, wherein the controller is configured to perform the following in response to detecting an uncorrectable error in a code word in a set of code words:
store bypass commands in the second set of queues to bypass processing subsequent code words read from the memory, wherein the subsequent code words are read from the memory in accordance with the instructions stored in the first set of queues;
store commands in the first set of queues to re-read the code word that had the uncorrectable error and the subsequent code words, wherein at least the code word with the uncorrectable error is re-read with a different read condition; and
store commands in the second set of queues to process the re-read code words.

19 . The storage module of claim 18 , wherein the controller is further configured to wait until all the code words have been re-read and processed before releasing any of the code words as a response to a read command.

20 . The storage module of claim 18 , wherein code words are processed by one or both of an error correction code engine and a decryption engine.

21 . The storage module of claim 18 , wherein the memory is a three-dimensional memory.

22 . The storage module of claim 18 , wherein the storage module is embedded in a host.

23 . The storage module of claim 18 , wherein the storage module is removably connected to a host.

24 . The storage module of claim 18 , wherein the storage module is a solid-state drive.

Assignees

• Sandisk Technologies Inc

Inventors

• Tuers Daniel E
• Weinberg Yoav
• Ryabinin Yuri

Classifications

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title