Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016043715-A1
Application number	US-201514814609-A
Country	US
Kind code	A1
Filing date	Jul 31, 2015
Priority date	Aug 8, 2014
Publication date	Feb 11, 2016
Grant date	—

Abstract

To generate an analog current without restriction by a power supply voltage. A semiconductor device includes a first node, a second node, a first- to an n-th-stage power storage element (n is an integer greater than or equal to 2), and a first- to an n-th-stage switch. The capacities of the first- to the n-th-stage power storage element are different from one another. The first- to the n-th-stage power storage element are electrically connected in parallel between the first node and the second node. A first terminal of a k-th stage power storage element (k is an integer greater than or equal to 1 and less than or equal to n) is electrically connected to the first input node via a k-th stage switch. The on/off states of the first- to the n-th-stage switch are controlled by a first to an n-th signal.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first node; a second node; a first-stage power storage element to a n-th-stage power storage element; and a first-stage switch to a n-th-stage switch, wherein capacities of the first-stage power storage element to the n-th-stage power storage element are different from one another, wherein the first-stage power storage element to the n-th-stage power storage element are electrically connected in parallel between the first node and the second node, wherein the first-stage power storage element to the n-th-stage power storage element are electrically connected to the first node via the first-stage switch to the n-th-stage switch, respectively, wherein n is an integer greater than or equal to 2, and wherein on/off states of the first-stage switch to the n-th-stage switch are controlled by a first signal to a n-th signal, respectively.

2 . The semiconductor device according to claim 1 ,
wherein the first stage switch to the n-th-stage switch each comprise a transistor, and on/off states of the first stage switch to the n-th-stage switch are controlled by the first signal to the n-th signal, respectively.

3 . The semiconductor device according to claim 1 ,
wherein the first stage switch to the n-th-stage switch each comprise a first transistor, a second transistor, and a capacitor, wherein a first terminal of each first transistor is electrically connected to a first terminal of each of the first-stage power storage element to the n-th-stage power storage element, respectively, wherein a second terminal of each first transistor is electrically connected to the first node, wherein a gate of each first transistor is electrically connected to the capacitor of each of the first stage switch to the n-th-stage switch, respectively, wherein each of the first signal to the n-th signal is input to a first terminal of each second transistor, respectively, wherein a second terminal of each second transistor is electrically connected to each gate of the first transistor, respectively, and wherein on/off states of second transistors of the first-stage switch to the n-th-stage switch are controlled by a common signal.

4 . The semiconductor device according to claim 3 ,
wherein a channel of each second transistor includes an oxide semiconductor.

5 . The semiconductor device according to claim 1 ,
wherein a capacity of the k-th-stage power storage element is 2 k-1 times the capacity of the first-stage power storage element, and wherein k is an integer greater than or equal to 1 and less than or equal to n.

6 . The semiconductor device according to claim 1 ,
wherein a signal group including the first signal to the n-th signal is a n-bit digital signal.

7 . An oscillator circuit, comprising q-stage inverter circuits,
wherein q is an odd number greater than 1 and less than n, wherein the q-stage inverter circuits are electrically connected in series, and wherein the semiconductor device according to claim 1 is electrically connected to each of input nodes of power supply voltages of the q-stage inverter circuits.

8 . A phase locked loop comprising the oscillator circuit according to claim 7 .

9 . A memory device comprising:
a memory cell array; and a row driver circuit and a column driver circuit configured to drive the memory cell array, wherein the column driver circuit includes the semiconductor device according to claim 1 .

10 . An electronic device comprising:
the semiconductor device according to claim 1 , and at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing.

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki
• Okamoto Yuki

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title