Method and circuit for reducing current surge

Patent metadata

Field	Value
Publication number	US-9299394-B2
Application number	US-201213645427-A
Country	US
Kind code	B2
Filing date	Oct 4, 2012
Priority date	Oct 4, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.

First claim

What is claimed is:

1. A power system, comprising:
a power switch configured to selectively connect a circuit to a power supply;
a storage capacitor;
a first capacitor switch configured to selectively connect the storage capacitor directly to a charge source;
a second capacitor switch configured to selectively connect the storage capacitor directly to the circuit; and
a power controller configured to turn on the first capacitor switch to charge the storage capacitor from the charge source, to turn off the first capacitor switch after the storage capacitor is charged, and, when the circuit is to be powered up, to turn on the power switch and the second capacitor switch to supply current to the circuit from the power supply and the storage capacitor, respectively, wherein the power controller is configured to turn off the second capacitor switch when an adjustable resistance of the power switch is set to a second resistance, being lower than a first resistance, after a time delay following an initial powering up of the circuit.

2. The power system of claim 1 , wherein the power controller is configured to initially set the resistance of the power switch to the first resistance when the circuit is to be powered up, and, after the time delay, to set the resistance of the power switch to the second resistance.

3. The power system of claim 2 , wherein the power switch comprises:
a first switch; and
a second switch, the second switch having a lower resistance than the first switch;

wherein the power controller is configured to set the resistance of the power switch to the first resistance by turning on the first switch, and to set the resistance of the power switch to the second resistance by turning on the second switch.

4. The power system of claim 1 , wherein, when the circuit is to be turned off or placed in a standby mode, the power controller is configured to turn off the power switch.

5. The power system of claim 1 , wherein the charge source is the power supply.

6. The power system of claim 1 , wherein the circuit comprises a memory, and the circuit is to be powered up from a memory retention voltage to a voltage of the power supply, the memory retention voltage being lower than the voltage of the power supply.

7. A method for managing power to a circuit, comprising:
charging a storage capacitor;
when the circuit is to be powered up, performing the steps of:
directly connecting, by turning on a power switch, the circuit to the power supply to supply current to the circuit from the power supply;
directly connecting, by turning on a capacitor switch, the circuit to the storage capacitor to supply current to the circuit from the storage capacitor;
disconnecting the storage capacitor from the circuit when an adjustable resistance of the power switch is set to a second resistance, being lower than a first resistance, after a time delay following an initial powering up of the circuit.

8. The method of claim 7 , further comprising:
initially setting the resistance of the power switch to the first resistance when the circuit is to be powered up; and
after the time delay, setting the resistance of the power switch to the second resistance.

9. The method of claim 7 , further comprising, when the circuit is to be turned off or placed in a standby mode, disconnecting the circuit from the power supply.

10. The method of claim 7 , wherein charging the storage capacitor comprises connecting the storage capacitor to the power supply.

Assignees

• Broadcom Corp

Inventors

• Upputuri Bharath
• Kauffmann Bruce
• Bloker Ray

Classifications

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• Y10T307/76

  Cross-Sectional Technologies · mapped topic

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title