Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016126888-A1
Application number	US-201514925161-A
Country	US
Kind code	A1
Filing date	Oct 28, 2015
Priority date	Oct 31, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

An object of the present invention is to provide a semiconductor device including an oscillator circuit including a circuit between inverters. In the circuit, a sum of the length (a 1 ) of a wiring path between a terminal A and a terminal C 1 and a length (b 1 ) of a wiring path between a terminal D 1 and a terminal B is substantially equal to a sum of the length (a 2 ) of a wiring path between the terminal A and a terminal C 2 and the length (b 2 ) of a wiring path between a terminal D 2 and the terminal B.

First claim

What is claimed is:

1 . A semiconductor device comprising an oscillator circuit comprising:
first to n-th inverters; a first circuit; and a second circuit, wherein n is an odd number of 3 or more, wherein a first terminal of the first circuit is electrically connected to an output terminal of the i-th inverter, wherein i is one of 1 to n−1, wherein a second terminal of the first circuit is electrically connected to an input terminal of the i+1-th inverter, wherein a first terminal of the second circuit is electrically connected to the output terminal of the i-th inverter, wherein a second terminal of the second circuit is electrically connected to the input terminal of the i+1-th inverter, and wherein a sum of a length of a wiring path between the output terminal of the i-th inverter and the first terminal of the first circuit and a length of a wiring path between the second terminal of the first circuit and the input terminal of the i+1-th inverter is substantially equal to a sum of a length of a wiring path between the output terminal of the i-th inverter and the first terminal of the second circuit and a length of a wiring path between the second terminal of the second circuit and the input terminal of the i+1-th inverter.

2 . The semiconductor device according to claim 1 , further comprising:
an insulating film over at least part of the first circuit and part of the second circuit; a first wiring over the insulating film, the first wiring being electrically connected to the output terminal of the i-th inverter; and a second wiring over the insulating film, the second wiring being electrically connected to the input terminal of the i+1-th inverter, wherein a first opening, a second opening, a third opening and a fourth opening are in the insulating film, wherein the first wiring is electrically connected to the first terminal of the first circuit through the first opening and to the first terminal of the second circuit through the second opening, wherein the second wiring is electrically connected to the second terminal of the first circuit through the third opening and to the second terminal of the second circuit through the fourth opening, and wherein a distance between the first opening and the second opening is substantially equal to a distance between the third opening and the fourth opening.

3 . The semiconductor device according to claim 1 , further comprising:
a first region in which the j-th inverter, where j is an odd number greater than or equal to 1 and less than or equal to n, is provided; a second region in which the first circuit and the second circuit are provided; and a third region in which the k-th inverter, where k is an even number greater than or equal to 2 and less than or equal to n−1, is provided, wherein the second region is positioned between the first region and the third region.

4 . The semiconductor device according to claim 1 ,
wherein the first circuit is configured to store first data, wherein the first circuit is configured to perform switching between a mode in which the first terminal and the second terminal are electrically disconnected from each other and a mode in which a resistance value between the first terminal and the second terminal is set to a value based on the first data, wherein the second circuit is configured to store second data, and wherein the second circuit is configured to perform switching between a mode in which the first terminal and the second terminal are electrically disconnected from each other and a mode in which a resistance value between the first terminal and the second terminal is set to a value based on the second data.

5 . The semiconductor device according to claim 1 ,
wherein the first data and the second data are each an analog potential.

6 . The semiconductor device according to claim 1 ,
wherein the first circuit comprises a first transistor and a first capacitor, wherein the second circuit comprises a second transistor and a second capacitor, wherein the first data is input to the first capacitor through the first transistor, wherein the second data is input to the second capacitor through the second transistor, wherein a channel formation region of each of the first transistor and the second transistor comprises an oxide semiconductor.

7 . The semiconductor device according to claim 1 ,
wherein the first circuit comprises a third transistor and a fourth transistor, wherein the second circuit comprises a fifth transistor and a sixth transistor, wherein the third transistor and the fourth transistor are electrically connected in series between the first terminal of the first circuit and the second terminal of the first circuit, wherein the fifth transistor and the sixth transistor are electrically connected in series between the first terminal of the second circuit and the second terminal of the second circuit, wherein a resistance value between a source and a drain of the third transistor is based on the first data, wherein the fourth transistor is configured to control conduction/non-conduction between the first terminal of the first circuit and the second terminal of the first circuit, wherein a resistance value between a source and a drain of the fifth transistor is based on the second data, and wherein the sixth transistor is configured to control conduction/non-conduction between the first terminal of the second circuit and the second terminal of the second circuit.

8 . The semiconductor device according to claim 1 , further comprising a PLL,
wherein the PLL comprises the oscillator circuit, a frequency divider, a phase comparator, and a loop filter.

9 . The semiconductor device according to claim 6 ,
wherein the oxide semiconductor of each of the first transistor and the second transistor comprises In, Zn and M, where M is Ga, Y, Zr, La, Ce, or Nd.

10 . An electronic device comprising the semiconductor device according to claim 1 .

11 . A semiconductor device comprising an oscillator circuit comprising:
a first inverter; a second inverter; a third inverter; a first circuit; and a second circuit, wherein a first terminal of the first circuit is electrically connected to an output terminal of the first inverter, wherein a second terminal of the first circuit is electrically connected to an input terminal of the second inverter, wherein a first terminal of the second circuit is electrically connected to the output terminal of the first inverter, wherein a second terminal of the second circuit is electrically connected to the input terminal of the second inverter, and wherein a sum of a length of a wiring path between the output terminal of the first inverter and the first terminal of the first circuit and a length of a wiring path between the second terminal of the first circuit and the input terminal of the second inverter is substantially equal to a sum of a length of a wiring path between the output terminal of the first inverter and the first terminal of the second circuit and a length of a wiring path between the second terminal of the second circuit and the input terminal of the second inverter.

12 . The semiconductor device according to claim 11 , further comprising:
an insulating film over at least part of the first circuit and part of the second circuit; a first wiring over the insulating film, the first wiring being electrically connected to the output terminal of the first inverter; and a second wiring over the insulating film, the second wiring being electrically connected to the input terminal of the second inverter, wherein a first opening, a second opening, a third opening

Assignees

• Semiconductor Energy Lab

Inventors

• Okamoto Yuki
• Kurokawa Yoshiyuki

Classifications

• H03K3/0315

  Ring oscillators · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H03B5/1228 Primary

  the amplifier comprising one or more field effect transistors · CPC title