Die structure, contact test structure, and contact testing method utilizing the contact test structure

US2016041201A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016041201-A1
Application numberUS-201414456827-A
CountryUS
Kind codeA1
Filing dateAug 11, 2014
Priority dateAug 11, 2014
Publication dateFeb 11, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A die structure is described, including a device area and a contact test area. The device area has therein a device structure including a first contact plug. The contact test area has therein a contact test structure that includes a second contact plug and is different from the device structure. The contact test structure is also described, including a well, a heavily doped region in the well, and a contact plug, wherein the heavily doped region and the well are both of N-type or are both of P-type, and the contact plug is disposed over the heavily doped region.

First claim

Opening claim text (preview).

What is claimed is: 1 . A die structure, comprising: a device area, having therein a device structure that includes a first contact plug; and a contact test area, having therein a contact test structure that includes a second contact plug and is different from the device structure. 2 . The die structure of claim 1 , wherein the contact test structure is different from the device structure in a doping structure in a semiconductor substrate under the contact plugs. 3 . The die structure of claim 2 , wherein the device structure comprises: a first heavily doped region of a first conductivity type, a first well of a second conductivity type in which the first heavily doped region is located, and the first contact plug, wherein the first contact plug is disposed over the first heavily doped region; and the contact test structure comprises: a second well, a second heavily doped region in the second well, and the second contact plug, wherein the second well and the second heavily doped region both have the first conductivity type or both have the second conductivity type, and the second contact plug is disposed over the second heavily doped region. 4 . The die structure of claim 3 , wherein the device structure further comprises an isolation layer beside the first heavily doped region, but the contact test structure does not include an isolation layer. 5 . The die structure of claim 3 , wherein the device structure further comprises an isolation layer beside the first heavily doped region, and the contact test structure further comprises the isolation layer beside the second heavily doped region. 6 . The die structure of claim 3 , wherein the device structure comprises a memory cell structure, and the first heavily doped region comprises a source/drain region. 7 . The die structure of claim 6 , wherein the memory cell structure comprises a flash memory cell structure. 8 . The die structure of claim 6 , wherein the first conductivity type is N-type, and the second conductivity type is P-type. 9 . A contact test structure, comprising: a well; a heavily doped region in the well, wherein the heavily doped region and the well are both of N-type or are both of P-type; and a contact plug, disposed over the heavily doped region. 10 . The contact test structure of claim 9 , which does not include an isolation layer. 11 . The contact test structure of claim 9 , further comprising an isolation layer beside the heavily doped region. 12 . A contact testing method, comprising: forming a contact test structure as described in claim 3 while forming a device structure as described in claim 3 ; irradiating the contact test structure with an electron beam; detecting secondary electrons released into or extracted from the second heavily doped region through the second contact plug; and determining the second contact plug to be good or bad according to an amount of the detected secondary electrons. 13 . The contact testing method of claim 12 , wherein the detection is in a retarding mode in which the released secondary electrons are detected. 14 . The contact testing method of claim 12 , wherein the detection is in an extracting mode in which the extracted secondary electrons are detected. 15 . The contact testing method of claim 12 , wherein the device structure comprises a memory cell structure, and the second heavily doped region comprises a source/drain region. 16 . The contact testing method of claim 15 , wherein the memory cell structure comprises a flash memory cell structure.

Assignees

Inventors

Classifications

  • Testing for continuity · CPC title

  • using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

  • G01R31/307Primary

    of integrated circuits · CPC title

  • Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00}) · CPC title

  • G01R1/07Primary

    Non contact-making probes · CPC title

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What does patent US2016041201A1 cover?
A die structure is described, including a device area and a contact test area. The device area has therein a device structure including a first contact plug. The contact test area has therein a contact test structure that includes a second contact plug and is different from the device structure. The contact test structure is also described, including a well, a heavily doped region in the well, …
Who is the assignee on this patent?
Macronix Int Co Ltd
What technology area does this patent fall under?
Primary CPC classification G01R31/307. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Feb 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).