Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9721857-B2
Application number	US-201615067173-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Dec 20, 2013
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a main surface which includes a first region and a second region;
a field effect transistor formed in the first region;
an element for voltage contrast inspection formed in the second region;
a first insulating film and a first semiconductor layer stacked on the first region sequentially;
a first gate electrode of the field effect transistor formed on the first semiconductor layer via a first gate insulating film;
first semiconductor regions formed in the first semiconductor layer so as to sandwich therebetween a channel region of the field effect transistor in the first semiconductor layer under the first gate electrode, one of the first semiconductor regions being a source region of the field effect transistor and another of the first semiconductor regions being a drain region of the field effect transistor;
first contact plugs respectively connected with the first semiconductor regions;
a second insulating film and a second semiconductor layer stacked on the second region sequentially;
a second gate electrode of the element for voltage contrast inspection formed directly over the second semiconductor layer via a second gate insulation film; and
second contact plugs respectively connected with the second semiconductor layer without a PN junction,
wherein the second semiconductor layer has no PN junction therein.

2. The semiconductor device according to claim 1 ,
wherein the first region is inside a chip region, and
wherein the second region is inside a scribe line region surrounding the chip region.

3. The semiconductor device according to claim 1 ,
wherein the first region and the second region are inside a chip region surrounded by a scribe line region.

4. The semiconductor device according to claim 1 ,
wherein first epitaxial layers are formed on the first semiconductor layer,
the first semiconductor regions are formed in the first epitaxial layers and the first semiconductor layer,
the first contact plugs are connected with the first semiconductor layer via the first epitaxial layers,
second epitaxial layers are formed on the second semiconductor layer, and
the second epitaxial layers and the second semiconductor layer have no PN junctions therein, and
the second contact plugs are connected with the second semiconductor layer via the second epitaxial layers.

5. The semiconductor device according to claim 4 ,
wherein first silicide layers are formed on the first epitaxial layers,
wherein second silicide layers are formed on the second epitaxial layers,
wherein the first contact plugs are connected with the first epitaxial layers via the first silicide layers, and
wherein the second contact plugs are connected with the second epitaxial layers via the second silicide layers.

6. The semiconductor device according to claim 5 , further comprising:
an insulating film covering the first gate electrode, the second gate electrode, the first silicide layers and the second silicide layers,
wherein the first contact plugs and the second contact plugs are formed in the insulating film.

7. The semiconductor device according to claim 1 ,
wherein the first contact plugs and the second contact plugs are comprised of a barrier conductor film containing Ti and TiN, and a main conductor film containing W.

8. The semiconductor device according to claim 1 , wherein the first and second regions each have a respective static random access memory structure.

9. The semiconductor device according to claim 1 ,
wherein the second gate electrode is between a pair of the second plugs in plan view, and
the second semiconductor layer between the pair of the second plugs in plan view and extending under the second gate electrode lacks a diffusion layer therein.

10. The semiconductor device according to claim 1 , wherein the element for voltage contrast inspection is a pseudo field effect transistor lacking a diffusion layer in the second semiconductor layer thereof.

Assignees

• Renesas Electronics Corp

Inventors

• Yamamoto Yoshiki
• Yoshida Tetsuya
• Sawai Koetsu

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title