Defect inspection method and defect inspection device

Patent metadata

Field	Value
Publication number	US-2016019682-A1
Application number	US-201414773319-A
Country	US
Kind code	A1
Filing date	Jan 27, 2014
Priority date	Mar 29, 2013
Publication date	Jan 21, 2016
Grant date	—

Abstract

In order to reduce the amount of time it takes to collect images of defects, this defect inspection device is provided with the following: a read-out unit that reads out positions of defects in a semiconductor wafer that have already been detected; a first imaging unit that takes, at a first magnification, a reference image of a chip other than the chip where one of the read-out defects is; a second imaging unit that takes, at the first magnification, a first defect image that contains the read-out defect; a defect-position identification unit that identifies the position of the defect in the first defect image taken by the second imaging unit by comparing said first defect image with the reference image taken by the first imaging unit; a third imaging unit that, on the basis of the identified defect position, takes a second defect image at a second magnification that is higher than the first magnification; a rearrangement unit that rearranges the read-out defects in an order corresponding to a path that goes through each of the read-out defects exactly once; and a stage-movement-path generation unit that selects the chip where the reference image corresponding to each defect is to be taken and generates a stage-movement path by determining stage-movement positions for the first and second imaging units.

First claim

1 . A defect inspection method comprising:
a reading-out step of reading out a plurality of positions of defects of a semiconductor wafer, the defects being detected beforehand by an inspection device; a first imaging step of, in capturing observation images of the defects read-out by the reading-out step, capturing, at a first magnification, a reference image of a chip other than a chip including the defect; a second imaging step of capturing, at the first magnification, a first defect image including the defect; a defect position identification step of identifying a defect position on the first defect image by comparing the reference image captured by the first imaging step with the first defect image captured by the second imaging step; and a third imaging step of capturing, as an observation image of the defect, a second defect image on the basis of the defect position identified by the defect position identification step and at a second magnification higher than the first magnification, and further comprising: a rearrangement step of rearranging the plurality of defects read-out by the reading-out step on the basis of the condition that one defect is observed only once when all the defects are observed; and a stage-movement-path generating step of generating a stage-movement path by selecting a chip imaged to capture the reference image, for each defect corresponding to the reference image, and determining stage-movement positions in the first imaging step and the second imaging step.

2 . The defect inspection method according to claim 1 , wherein the chip imaged to capture the reference image is selected among a chip including a defect imaged just before imaging the reference image, and a chip adjacent to the chip.

3 . The defect inspection method according to claim 2 , wherein a chip imaged to capture the reference image is selected among a chip including a defect imaged just before imaging the reference image, and a chip adjacent to the chip, and is selected so that the distance between the imaging position of the reference image and the defect position imaged just before imaging the reference image is shortest.

4 . The defect inspection method according to claim 2 , wherein a chip imaged to capture the reference image is selected among a chip including a defect imaged just before imaging the reference image, and a chip adjacent to the chip, and is selected so that the distance between the imaging position of the reference image and the defect position imaged just before imaging the reference image is shortest in a predetermined distance or more.

5 . The defect inspection method according to claim 1 , wherein a chip imaged to capture the reference image is a chip including a defect imaged just before imaging the reference image.

6 . The defect inspection method according to claim 5 , wherein, when the distance between the imaging position of the reference image and the defect position imaged just before imaging the reference image is less than or not more than a predetermined distance, a chip adjacent to the chip including the defect imaged just before imaging the reference image is selected as a chip imaged to capture the reference image.

7 . The defect inspection method according to claim 1 , wherein a chip including the imaging position of the reference image is a chip selected so that the sum of the distance between the defect position imaged just before imaging the reference image and the imaging position of the reference image, and the distance between the imaging position of the reference image and the defect position imaged just after imaging the reference image.

8 . The defect inspection method according to claim 7 , wherein a chip including the imaging position of the reference image is selected among a chip including the defect imaged just before imaging the reference image, and a chip adjacent to the chip.

9 . The defect inspection method according to claim 8 , wherein, when the distance between the imaging position of the reference image and the defect position imaged just before imaging the reference image is less than or not more than a predetermined distance, a chip imaged to capture the reference image is selected among chips adjacent to the chip including the defect imaged just before imaging the reference image.

10 . The defect inspection method according to claim 1 , wherein, in the stage-movement-path generation step, a chip imaged to capture the reference image in the first imaging step is selected among a chip including the defect imaged just before imaging the reference image, and a chip adjacent to the chip.

11 . The defect inspection method according to claim 10 , wherein a chip imaged to capture the reference image is selected among a chip including the defect imaged just before imaging the reference image, and chips adjacent to the chip and located so that the distance between the imaging position of the reference image and the defect position imaged just before imaging the reference image is shortest.

12 . The defect inspection method according to claim 10 , wherein a chip imaged to capture the reference image is selected among a chip including the defect imaged just before imaging the reference image, and a chip adjacent to the chip, and is selected such that the distance between the imaging position of the reference image and the defect position imaged just before imaging the reference image is shortest in a distance not less than a predetermined distance.

13 . The defect inspection method according to claim 1 , wherein, in the stage-movement-path generation step, a chip including the defect imaged just before imaging the reference image is set as a chip imaged to capture the reference image in the first imaging step.

14 . The defect inspection method according to claim 13 , wherein, when the distance between the imaging position of the reference image and the defect position imaged just before imaging the reference image is less than or not more than a predetermined distance, a chip imaged to capture the reference image is selected among chips adjacent to the chip including the defect imaged just before imaging the reference image.

15 . The defect inspection method according to claim 1 , wherein, in the stage-movement-path generation step, a chip which is located so that the sum of the distance between the defect position imaged just before imaging the reference image and the imaging position of the reference image, and the distance between the imaging position of the reference image and the defect position imaged just after imaging the reference image is smallest, is set as a chip including the imaging position of the reference image in the imaging step.

16 . The defect inspection method according to claim 15 , wherein a chip including the imaging position of the reference image is selected among a chip including the defect imaged just before imaging the reference image, and a chip adjacent to the chip.

17 . The defect inspection method according to claim 16 , wherein, when the distance between the imaging position of the reference image and the defect position imaged just before imaging the reference image is less than or not more than a predetermined distance, a chip imaged to capture the reference image is selected among chips adjacent to the chips including the defect imaged just before imaging the reference image.

18 . The defect inspection method according to claim 1 , wherein, when the distance between the imaging position of the reference image and the defect position imaged just after imaging the refe

Assignees

• Hitachi High Tech Corp

Inventors

• Takagi Yuji
• Harada Minoru
• Sakamoto Masashi
• Hirai Takehiro

Classifications

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G06F18/2433

  Single-class perspective, e.g. one-against-all classification; Novelty detection; Outlier detection · CPC title

• G06V10/751

  Comparing pixel values or logical combinations thereof, or feature values having positional relevance, e.g. template matching · CPC title

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• G06K9/6202

  Physics · mapped topic