Semiconductor structure with integrated passive structures

Patent metadata

Field	Value
Publication number	US-2016013093-A1
Application number	US-201514864080-A
Country	US
Kind code	A1
Filing date	Sep 24, 2015
Priority date	Sep 26, 2012
Publication date	Jan 14, 2016
Grant date	—

Abstract

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

First claim

What is claimed:

1 . A method comprising:
forming a layered structure comprising:
forming a high-k dielectric material on a substrate;
forming a metal material on the high-k dielectric material;
forming a semiconductor material over the metal material; and
forming a masking layer over the semiconductor material;
patterning the layered structure to form a stacked structure in an active region; forming shallow trench isolation (STI) structures adjacent to the stacked structure in the active region; removing the masking layer, after the formation of the STI structures; forming a semiconductor layer directly on the STI structures and the semiconductor material of the stacked structure; forming at least one passive structure by patterning of the semiconductor layer; and forming an active device by the patterning of the semiconductor layer and the stacked structure.

2 . The method of claim 1 , further comprising fine tuning the semiconductor layer prior to the forming of the active device and the passive structure.

3 . The method of claim 1 , further comprising implanting regions after the forming of the semiconductor layer, wherein the implanting is of such a concentration and energy that it penetrates through the stacked structure into the substrate of the active region.

4 . The method of claim 1 , wherein a top surface of the STI structures and the semiconductor material are planar by etching the masking layer of the layered structured and part of the STI structure.

5 . The method of claim 1 , further comprising forming a liner on the stacked structure, prior to the forming of the STI structures, wherein:
the stacked structure is patterned prior to the formation of the STI structures; and the active device is formed with a height higher than the passive structure.

6 . The method of claim 5 , further comprising forming an insulating layer over and between the active device and the passive structure, wherein the forming of the insulating layer is devoid of keyholes due to an aspect ratio between the passive structure and the active device.

7 . The method of claim 1 , wherein the STI structures are non-planar over the stacked structure in the active region.

8 . The method of claim 7 , wherein the STI structures are formed by using an underfill of region resulting in protrusion of semiconductor material over the stacked structure in the active region.

9 . The method of claim 8 , wherein the protrusion is planarized to form planar STI structures.

10 . The method of claim 7 , wherein the STI structures are formed by using an overfill of region resulting in a recess of semiconductor material over the stacked structure in the active region.

11 . The method of claim 10 , wherein the semiconductor material is planarized to form planar STI structures.

12 . The method of claim 1 , wherein the high-k dielectric material is a hafnium based material.

13 . A method, comprising:
forming a high-k dielectric material on a semiconductor material; forming a metal gate material on the high-k material; forming a semiconductor layer on the metal gate material; forming a stacked structure in an active region by patterning the semiconductor material, high-k dielectric material, metal gate material and semiconductor layer; forming a liner on a top and side surfaces of the stacked structure in the active region, and exposed surfaces of a buried oxide layer or bulk silicon; forming an insulator layer over the liner; planarizing the insulator layer to form insulator regions, separated by the stacked structure formed in the active region; recessing the insulator regions to form STI structures; forming a second semiconductor material over the STI structures and the semiconductor layer of the stacked structure in the active region; and performing well implantation processes through the second semiconductor material.

14 . The method of claim 13 , wherein the metal gate material is one of TiN, TaN, Al, and W deposited to a thickness ranging from about 1 nm to about 200 nm.

15 . The method of claim 13 , wherein the semiconductor layer is polysilicon or amorphous silicon, and is 5 nm to 200 nm in thickness.

16 . The method of claim 13 , wherein the patterning is two or more reactive ion chemistries.

Assignees

• IBM

Inventors

• Chou Anthony I
• Kumar Arvind
• Mo Renee T
• Narasimha Shreesh

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P70/237

  the processing being a planarisation of insulating layers · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title