Method and system for asynchronous successive approximation analog-to-digital convertor (adc) architecture

Patent metadata

Field	Value
Publication number	US-2016006450-A1
Application number	US-201514812327-A
Country	US
Kind code	A1
Filing date	Jul 29, 2015
Priority date	Jul 18, 2012
Publication date	Jan 7, 2016
Grant date	—

Abstract

Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.

First claim

1 - 20 . (canceled)

21 . A method, comprising:
in signal processing circuitry:
searching through a plurality of quantization levels for a quantization level that matches an analog input; and
when said search for said matching quantization level fails within a particular amount of time, adjusting at least a portion of an output of said signal processing circuitry.

22 . The method of claim 21 , wherein adjusting at least a portion of an output of said signal processing circuitry comprises setting at least said portion of said output of said signal processing circuitry to a predefined value.

23 . The method of claim 22 , comprising selecting said predefined value based on an outcome of processing in said signal processing circuitry prior to or when said search for said matching quantization level fails.

24 . The method of claim 21 , comprising selecting, for adjusting at least a portion of an output of said signal processing circuitry, between an output of a normal processing path and an output of a code generation path configured for handling search failures.

25 . The method of claim 21 , wherein at least said portion of said output comprises a sequence of bits.

26 . The method of claim 25 , wherein said sequence of bits corresponds to remaining bits in a N-bit output, starting with bit corresponding to the failing in said search for said matching quantization level.

27 . The method of claim 26 , wherein the value of N is determined, when said signal processing circuitry comprises an analog-to-digital convertor (ADC), based on resolution of said ADC.

28 . The method of claim 21 , wherein said signal processing circuitry comprises an asynchronous successive approximation register (SAR) analog-to-digital convertor (ADC).

29 . The method of claim 21 , comprising generating timing information that is used in controlling generating of said output of said signal processing circuitry.

30 . The method of claim 29 , comprising utilizing said timing information in measuring per-cycle operation time during said searching through said plurality of quantization levels.

31 . A system, comprising:
signal processing circuitry that is operable to:
search through a plurality of quantization levels for a quantization level that matches an analog input; and
when said search for said matching quantization level fails within a particular amount of time, adjust at least a portion of an output of said signal processing circuitry.

32 . The system of claim 31 , wherein said signal processing circuitry is operable to set at least said portion of said output of said signal processing circuitry, when adjusting it, to a predefined value.

33 . The system of claim 32 , wherein said signal processing circuitry comprises a code generator circuit for generating said predefined value.

34 . The system of claim 33 , wherein said code generator circuit is operable to generate said predefined value based on an outcome of processing in said signal processing circuitry prior to or when said search for said matching quantization level fails.

35 . The system of claim 31 , wherein said signal processing circuitry comprises a selector circuit for use in setting at least said portion of an output of said signal processing circuitry.

36 . The system of claim 35 , wherein said selector circuit is operable to select between output of a normal processing path in said signal processing circuitry and an output of a generator circuit that is operable to generate a particular output when searches fail.

37 . The system of claim 35 , wherein said selector circuit is operable to select on per-bit basis, to enable setting only a sequence of bits, corresponding to a portion of an overall N-bit output, based on said output of said generator circuit.

38 . The system of claim 37 , wherein the value of N is determined, when said signal processing circuitry comprises an analog-to-digital convertor (ADC), based on resolution of said ADC.

39 . The system of claim 30 , wherein said signal processing circuitry comprises a timing generator circuit that is operable to generate timing information for use in controlling generating said output of said signal processing circuitry.

40 . The method of claim 38 , wherein said signal processing circuitry is operable to utilize said timing information in measuring per-cycle operation time during said searching through said plurality of quantization levels.

Assignees

• Maxlinear Inc

Inventors

• Chen Xuefeng
• Chan Kok Lim
• Fogleman Eric
• Ye Sheng

Classifications

• H03M1/0682 Primary

  using a differential network structure, i.e. symmetrical with respect to ground · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/38 Primary

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/125

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title

• H03M1/06

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title